Daisaburo Takashima

发表

Open/folded bit-line arrangement for ultra-high-density DRAM's

Yukihito Oowaki, Kazunori Ohuchi, Daisaburo Takashima, 1994 .

A 7T-SRAM With Data-Write Technique by Capacitive Coupling

Daisaburo Takashima, Kazuhiro Shimazaki, Masato Endo, 2019, IEEE Journal of Solid-State Circuits.

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes

Tohru Ozaki, Yuki Yamada, Tohru Furuyama, 2010, IEEE Journal of Solid-State Circuits.

A 1.6GB/s DDR2 128Mb chain FeRAM with scalable octal bitline and sensing schemes

Tohru Ozaki, Yuki Yamada, Tohru Furuyama, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's

Yukihito Oowaki, Daisaburo Takashima, Kazuya Ohuchi, 1998 .

Highly relaible reference bitline bias designs for 64Mb and 128Mb chain FeRAMs

Daisaburo Takashima, Hidehiro Shiga, Ryu Ogiwara, 2010, 2010 IEEE Asian Solid-State Circuits Conference.

Implementation of sub-10 ns serial access mode to a standard 64-Mb DRAM

Shigeyoshi Watanabe, Yukihito Oowaki, Daisaburo Takashima, 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

Word-line architecture for highly reliable 64-Mb DRAM

Yukihito Oowaki, Daisaburo Takashima, Shigeyoshi Watanabe, 1992 .

28.9 An Embedded DRAM Technology for High

Daisaburo Takashima, Hiroshi Sukegawa, Noboru Shibata, 2011 .

A 100MHz ladder FeRAM design with capacitance-coupled-bitline (CCB) cell

Tohru Ozaki, Daisaburo Takashima, Yasushi Nagadomi, 2010, 2010 Symposium on VLSI Circuits.

Dynamic semiconductor memory device having a twisted bit line

Yukihito Oowaki, Daisaburo Takashima, Kenji Tsuchida, 1990 .

A novel power-off mode for a battery-backup DRAM

Y. Oowaki, Daisaburo Takashima, 1997 .

Folded-read And Open/folded-restore Bit-line Scheme For Giga Scale 6f2 Dram Cell

Shigeyoshi Watanabe, Tohru Ozaki, Yukihito Oowaki, 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

A cell transistor scalable DRAM array architecture

Daisaburo Takashima, H. Nakano, 2002 .

A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs

Tohru Ozaki, Akihiro Nitayama, Ryo Fukuda, 2011, IEEE Journal of Solid-State Circuits.

A 128Mb ChainFeRAMTM and system designs for HDD application and enhanced HDD performance

Daisaburo Takashima, Yohji Watanabe, Yasushi Nagadomi, 2009, 2009 IEEE Asian Solid-State Circuits Conference.

Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs

Daisaburo Takashima, Shinichiro Shiratake, Hidehiro Shiga, 2015, IEEE Journal of Solid-State Circuits.

An embedded DRAM technology for high-performance NAND flash memories

Daisaburo Takashima, Hiroshi Sukegawa, Noboru Shibata, 2011, 2011 IEEE International Solid-State Circuits Conference.

A 128 Mb Chain FeRAM and System Design for HDD Application and Enhanced HDD Performance

Daisaburo Takashima, Yohji Watanabe, Yasushi Nagadomi, 2011, IEEE Journal of Solid-State Circuits.

A 100 MHz Ladder FeRAM Design With Capacitance-Coupled-Bitline (CCB) Cell

Tohru Ozaki, Daisaburo Takashima, Yasushi Nagadomi, 2011, IEEE Journal of Solid-State Circuits.

Folded Bitline Architecture for a Gigabit-Scale NAND DRAM (Special Issue on Circuit Technologies for Memory and Analog LSIs)

Yukihito Oowaki, Kazunori Ohuchi, Daisaburo Takashima, 1997 .

A 7T-SRAM with data-write technique by capacitive coupling

Daisaburo Takashima, Kazuhiro Shimazaki, Masato Endo, 2015, 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Overview and Trend of Chain FeRAM Architecture

Daisaburo Takashima, 2001 .

Word-line Architecture For Constant Reliability 64Mb DRAM

Yukihito Oowaki, Daisaburo Takashima, Shigeyoshi Watanabe, 1991, 1991 Symposium on VLSI Circuits.

A 33ns 64Mb DRAM

Shigeyoshi Watanabe, Fumio Horiguchi, Yukihito Oowaki, 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

A scalable shield-bitline-overdrive technique for 1.3V Chain FeRAM

Tohru Ozaki, Akihiro Nitayama, Ryo Fukuda, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

An Embedded DRAM Technology for High-Performance NAND Flash Memories

Daisaburo Takashima, Hiroshi Sukegawa, Noboru Shibata, 2012, IEEE Journal of Solid-State Circuits.

The stabilized reference-line (SRL) technique for scaled DRAMs

Yukihito Oowaki, Fujio Masuoka, Daisaburo Takashima, 1990 .

High-density chain ferroelectric random access memory (chain FRAM)

Daisaburo Takashima, I. Kunishima, 1997 .

Overview of FeRAMs: Trends and perspectives

Daisaburo Takashima, D. Takashima, 2011, 2011 11th Annual Non-Volatile Memory Technology Symposium Proceeding.

10-2 Stand-by/Active Mode Logic for Sub-I V 1G/4Gb DRAMs

Shigeyoshi Watanabe, Kazunori Ohuchi, Daisaburo Takashima, 1992 .

A sub-40-ns chain FRAM architecture with 7-ns cell-plate-line drive

Yukihito Oowaki, Daisaburo Takashima, Susumu Shuto, 1999 .

A 33-ns 64-Mb DRAM

Fumio Horiguchi, Yukihito Oowaki, Shigeyoshi Watanabe, 1991 .