Shigeyoshi Watanabe

发表

Open/folded bit-line arrangement for ultra-high-density DRAM's

Yukihito Oowaki, Kazunori Ohuchi, Daisaburo Takashima, 1994 .

Study of pattern area reduction with FinFET and SGT for LSI

Takahiro Kodama, Shigeyoshi Watanabe, Yu Hiroshima, 2013 .

Analysis of bit cost for stacked type MRAM with NAND structured cell

Shigeyoshi Watanabe, Shoto Tamai, 2013 .

Process step and analysis of bit cost for stacked type MRAM with NOR structured cell

Shigeyoshi Watanabe, Shoto Tamai, 2015 .

Design method of stacked type MRAM with NAND structured cell

Shigeyoshi Watanabe, Shoto Tamai, 2013 .

Analysis of pattern area reduction for logic circuit and system LSI with SGT

Shigeyoshi Watanabe, Tomohiro Yokota, 2015 .

Circuit design of reconfigurable dynamic logic based on double gate cntfets focusing on number of states of back gate voltages

Manabu Kobayashi, Yasuyuki Miura, Shigeyoshi Watanabe, 2014 .

Proposal of Vertical Stacked Type Fe-FET NAND/NAND Array and Its Application to Logic LSI

Shigeyoshi Watanabe, Shigeyoshi Watanabe, Tomohiro Yokota, 2016 .

Design methodology for system LSI with TIS (trench‐isolated transistor using sidewall gate)

Shigeyoshi Watanabe, S. Watanabe, 2006 .

Word-line architecture for highly reliable 64-Mb DRAM

Yukihito Oowaki, Daisaburo Takashima, Shigeyoshi Watanabe, 1992 .

Novel cell array noise cancelling design scheme for stacked type MRAM with NAND structured cell

Shigeyoshi Watanabe, Shoto Tamai, S. Watanabe, 2013 .

Design Technology of Stacked Type Chain PRAM

Sho Kato, Shigeyoshi Watanabe, 2013 .

Impact of three-dimensional transistor on the pattern area reduction for ULSI

Shigeyoshi Watanabe, 2003 .

Proposal of Stacked Type Memory/Logic Circuit Array and Its Application to LUT (Look Up Table)

Shigeyoshi Watanabe, Shoto Tamai, Takumi Sato, 2016 .

Circuit design of 2-input reconfigurable dynamic logic based on stacked type Fe-FET with whole set of 16 functions

Shigeyoshi Watanabe, Tomohiro Yokota, 2017 .

Storage Systems for Image Information Media. Semiconductor Memory.

Shigeyoshi Watanabe, 1996 .

Word-line Architecture For Constant Reliability 64Mb DRAM

Yukihito Oowaki, Daisaburo Takashima, Shigeyoshi Watanabe, 1991, 1991 Symposium on VLSI Circuits.

Analysis of bit cost and performance for stacked type chain PRAM

Sho Kato, Shigeyoshi Watanabe, Sho Kato, 2013 .

Circuit Design of 2-Input Reconfigurable Dynamic Logic Based on Double Gate MOSFETs with Whole Set of 16 Functions

Manabu Kobayashi, Yasuyuki Miura, Shigeyoshi Watanabe, 2014 .

Low cost stacked type NOR MRAM with 1 MOSFET/1 MTJ cell structure and shared source line (SL) scheme

Shigeyoshi Watanabe, Shoto Tamai, 2015 .

Diagonal layout and surface strap trench (DST) cell [embedded DRAMs]

Mitsuru Sato, Shigeyoshi Watanabe, Takeshi Hamamoto, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

A New On-Chip Voltage Converter for Submicron High-Density DRAMs

Tohru Furuyama, Takashi Ohsawa, Shigeyoshi Watanabe, 1986, ESSCIRC '86: Twelfth European Solid-State Circuits Conference.

Design Method of Stacked Type NAND MRAM with Ultra Low Bit Cost

Shigeyoshi Watanabe, Shoto Tamai, 2013 .

Design method of stacked type thermally assisted MRAM with NAND structured cell

Shigeyoshi Watanabe, Shoto Tamai, S. Watanabe, 2013 .

An 18.5ns 128MB SOI DRAM with a floating body cell

Takashi Ohsawa, Shigeyoshi Watanabe, Takeshi Hamamoto, 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

History and Future Trend of Semiconductor Memory

Shigeyoshi Watanabe, 2009 .

Proposal of stacked type Fe-FET reconfigurable logic circuit featured with parallel processing within one silicon pillar using modified process technology of 3D NAND flash memory

Shigeyoshi Watanabe, Tomohiro Yokota, 2018 .

The stabilized reference-line (SRL) technique for scaled DRAMs

Yukihito Oowaki, Fujio Masuoka, Daisaburo Takashima, 1990 .

Design Scheme Considering Memory Cell Array Noise for Stacked Type MRAM with NAND Structured Cell

Shigeyoshi Watanabe, Shoto Tamai, S. Watanabe, 2013 .