Takahiro Watanabe

发表

J1010505 Study on Acceleration Reduction Device of Vibration Isolation Bed for Ambulance : Redesign and Improvement of Variable Friction Damper

Takahiro Watanabe, Masanori Shintani, Yuji Ogawa, 2014 .

A-3-5 Line-sweeping Based IO Assignment and Diagonal Routing

Takahiro Watanabe, Xin He, Ran Zhang, 2014 .

A performance enhanced adaptive routing algorithm for 3D Network-on-Chips

Takahiro Watanabe, Xin Jiang, Lian Zeng, 2015, TENCON 2015 - 2015 IEEE Region 10 Conference.

Laser-driven high-energy ion generation for a compact cancer therapy accelerator

Takahiro Watanabe, Mitsuru Uesaka, Zhong Li, 2003, European Conference on Laser Interaction with Matter.

Fault-tolerant image filter design using GA

Takahiro Watanabe, Fangfang Wang, Xiaoming Zhao, 2010, TENCON 2010 - 2010 IEEE Region 10 Conference.

Vertical-mesh-conscious-dynamic routing algorithm for 3D NoCs

Takahiro Watanabe, Xin Jiang, Lian Zeng, 2015, TENCON 2015 - 2015 IEEE Region 10 Conference.

Real Time Gesture Recognition Using Eigenspace from Multi Input Image Sequence

Takahiro Watanabe, Masahiko Yachida, M. Yachida, 1999, IEEE International Conference on Automatic Face & Gesture Recognition.

An Efficient Highly Adaptive and Deadlock-Free Routing Algorithm for 3D Network-on-Chip

Takahiro Watanabe, Xin Jiang, Lian Zeng, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

An FPGA Connect6 Solver with a two-stage pipelined evaluation

Takahiro Watanabe, Minoru Watanabe, Takashi Yoza, 2011, 2011 International Conference on Field-Programmable Technology.

Low-Cost Congestion Detection Mechanism for Networks-on-Chip

Takahiro Watanabe, Xin Jiang, Zhengqian Han, 2019, 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC).

Real-time gesture recognition from dynamic images for construction of any interactive system: Application to a virtual conductor system

Takahiro Watanabe, Masahiko Yachida, Chil-Woo Lee, 1998, Systems and Computers in Japan.

Othello Solver based on a soft-core MIMD processor array

Takahiro Watanabe, Minoru Watanabe, Retsu Moriwaki, 2010, 2010 International Conference on Field-Programmable Technology.

Application-specific shared last-level cache optimization for low-power embedded systems

Takahiro Watanabe, Huatao Zhao, Jiongyao Ye, 2015, 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS).

Coordinated movement algorithm for accompanying cane robot

Takahiro Watanabe, Yasuhisa Hasegawa, Shunki Itadera, 2016, 2016 International Symposium on Micro-NanoMechatronics and Human Science (MHS).

High Performance Virtual Channel Based Fully Adaptive 3D NoC Routing for Congestion and Thermal Problem

Takahiro Watanabe, Xin Jiang, Lian Zeng, 2017, IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences.

A hybrid architecture for efficient FPGA-based implementation of multilayer neural network

Yiping Dong, Zhen Lin, Takahiro Watanabe, 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

A-3-2 A Parallel Routing Method using Virtual Boundary

Takahiro Watanabe, Ran Zhang, Takahiro Watanabe, 2012 .

New power-aware placement for region-based FPGA architecture combined with dynamic power gating by PCHM

Yiping Dong, Takahiro Watanabe, Ce Li, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

Real time gesture recognition using eigenspace from multi-input image sequences

Takahiro Watanabe, Masahiko Yachida, M. Yachida, 1998, Proceedings Third IEEE International Conference on Automatic Face and Gesture Recognition.

The Real-Time and Embedded Soccer Robot Control System

Takahiro Watanabe, Hang Li, Zhenyu Wu, 2010 .

A Clocking Scheme for Lowering Peak-Current in Dynamic Logic Circuits

Takahiro Watanabe, Tadao Nakamura, Hiroyuki Matsubara, 2000 .

Behavior-Aware cache hierarchy optimization for low-power multi-core embedded systems

Takahiro Watanabe, Chen Zhu, Xiao Luo, 2017 .

An approximation algorithm for the hamiltonian walk problem on maximal planar graphs

Takahiro Watanabe, Takao Asano, Takao Nishizeki, 1983, Discret. Appl. Math..

Pseudo Dual Path Processing to reduce the branch misprediction penalty in embedded processors

Takahiro Watanabe, Yuxin Sun, Huatao Zhao, 2013, 2013 IEEE 10th International Conference on ASIC.

Generating even triangulations of the projective plane

Takahiro Watanabe, Yusuke Suzuki, 2007, J. Graph Theory.

PWSF: Planar-west-South-first routing algorithm for 3D Network-on-Chip

Takahiro Watanabe, Xin Jiang, Renjie Li, 2017, TENCON 2017 - 2017 IEEE Region 10 Conference.

Identifying contents page of documents

Takahiro Watanabe, Qin Luo, Takeshi Nakayama, 1996, Proceedings of 13th International Conference on Pattern Recognition.

High speed implementation of the keyed-hash message authentication code (HMAC) based on SHA-1 algorithm

Takahiro Watanabe, S. Suhaili, 2017 .

Evaluating Dialogue Strategies under Communication Errors Using Computer-to-Computer Simulation

Takahiro Watanabe, Masahiro Araki, Shuji Doshita, 1998 .

Developing a Real-Time System for Measuring the Consumption of Seasoning

Takahiro Watanabe, Atsushi Hashimoto, Michihiko Minoh, 2011, 2011 IEEE International Symposium on Multimedia.

Simulation-Based Power Estimation of Low Power MD5 Design Techniques

Takahiro Watanabe, S. Suhaili, 2016 .

DS-1-3 DESIGN AND IMPLEMENTATION OF SHA-1 HASH FUNCTION USING VERILOG HDL

Takahiro Watanabe, S. Suhaili, Takahiro Watanabe, 2012 .

A New Recovery Mechanism in Superscalar Microprocessors by Recovering Critical Misprediction

Takahiro Watanabe, Yu Wan, Jiongyao Ye, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Towards Secure Authentication between Human and Computer

Takahiro Watanabe, Sozo Inoue, Hiroto Yasuura, 2006 .

High performance and low latency mapping for neural network into network on chip architecture

Yiping Dong, Zhen Lin, Takahiro Watanabe, 2009, 2009 IEEE 8th International Conference on ASIC.

A Framework for Feature Extraction of Images by Energy Minimization (Special Issue on Computer Vision)

Takahiro Watanabe, Satoshi Nakagawa, Yuji Kuno, 1994 .

A Multiprocessor System for a Small Size Soccer Robot Control System

Takahiro Watanabe, Yang Jiang, Zhenyu Wu, 2008, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008).

0.18-um CMOS Process Highly Sensitive Differential Optically Reconfigurable Gate Array VLSI

Takahiro Watanabe, Minoru Watanabe, 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

New power-efficient FPGA design combining with region-constrained placement and multiple power domains

Yiping Dong, Takahiro Watanabe, Ce Li, 2011, 2011 IEEE 9th International New Circuits and systems conference.

A low-power misprediction recovery mechanism

Takahiro Watanabe, Jiongyao Ye, 2009, 2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia).

Efficient GA Approach Combined with Taguchi Method for Mixed Constrained Circuit Design

Takahiro Watanabe, Fangfang Wang, Zhiguo Bao, 2011, 2011 International Conference on Computational Science and Its Applications.

A novel Genetic Algorithm with cell crossover for circuit design optimization

Takahiro Watanabe, Zhiguo Bao, 2009, 2009 IEEE International Symposium on Circuits and Systems.

Encoding and decoding digital signals

Takahiro Watanabe, Kenzo Akagiri, Osamu Shimoyoshi, 1993 .

Design of high-throughput SHA-256 hash function based on FPGA

Takahiro Watanabe, Shamsiah binti Suhaili, Takahiro Watanabe, 2017, 2017 6th International Conference on Electrical Engineering and Informatics (ICEEI).

High performance Networks on Chip architecture with a new routing strategy for neural network

Yiping Dong, Zhen Lin, Takahiro Watanabe, 2010, 2010 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia).

Fault-tolerant image filter design using particle swarm optimization

Takahiro Watanabe, Fangfang Wang, Xiaoming Zhao, 2011, Artificial Life and Robotics.

Real Time Gesture Recognition in A Real Complex Environment Using Interactive Model Generation

Takahiro Watanabe, Masahiko Yachida, Kuniteru Sakakibara, 1999 .

A performance enhanced dual-switch Network-on-Chip architecture

Takahiro Watanabe, Xin Jiang, Lian Zeng, 2015, The 20th Asia and South Pacific Design Automation Conference.

D-6-11 TRAFFIC BALANCE PARTIAL ADAPTIVE ROUTING ALGORITHM for 3D NETWORK-on-CHIP

Takahiro Watanabe, Lian Zeng, Zhu Xia, 2015 .

Modeling RFID Information Systems for the Reliability

Takahiro Watanabe, Sozo Inoue, Hiroto Yasuura, 2004 .

Circuit Design Optimization Using Genetic Algorithm with Parameterized Uniform Crossover

Takahiro Watanabe, Zhiguo Bao, 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A 16-laser array for an optically reconfigurable gate array

Takahiro Watanabe, Minoru Watanabe, 2011, 2011 International Conference on Space Optical Systems and Applications (ICSOS).

COST ALLOCATION ON VEHICLE ROUTING PROBLEM

Takahiro Watanabe, Mikio Kubo, Masao Mori, 1997 .

FPGA Blokus Duo Solver using a massively parallel architecture

Takahiro Watanabe, Minoru Watanabe, Hiroyuki Ito, 2013, 2013 International Conference on Field-Programmable Technology (FPT).

High Throughput Implementation of RIPEMD-160 using Unfolding Transformation

Takahiro Watanabe, Suhaili Shamsiah binti, Binti Huja Husin Maimun, 2018 .

Automatic Viewing System for a Vast Number of DRC Errors using Agglomerative Hierarchical Clustering

Takahiro Watanabe, Tomoki Kamei, 2015 .

Real-time gesture recognition using Maskable Template Model

Takahiro Watanabe, Masahiko Yachida, Chil-Woo Lee, 1996, Proceedings of the Third IEEE International Conference on Multimedia Computing and Systems.

High performance virtual channel based fully adaptive thermal-aware routing for 3D NoC

Takahiro Watanabe, Xin Jiang, Lian Zeng, 2017, 2017 18th International Symposium on Quality Electronic Design (ISQED).

A novel fully adaptive fault-tolerant routing algorithm for 3D Network-on-Chip

Takahiro Watanabe, Xin Jiang, 2013, 2013 IEEE International Conference of IEEE Region 10 (TENCON 2013).

0.18 μm CMOS proess high-sensitivity optially reonfgurable gatearray VLSI

Takahiro Watanabe, Minoru Watanabe, 2012, CARN.

Information processing program, an information processing system, information processing apparatus, an information processing method

Takahiro Watanabe, 毛呂功, Isao Moro, 2011 .

High-Throughput Message Digest (MD5) Design and Simulation-Based Power Estimation Using Unfolding Transformation

Takahiro Watanabe, S. Suhaili, 2017 .

Application of automatic parallel fracturing system on hierarchical and large data structure

Takahiro Watanabe, Eiji Tsujimoto, Keitaro Katabuchi, 2002, SPIE Photomask Technology.

Generation of 5-Axis Control Collision-Free Tool Path and Postprocessing for NC Data

Takahiro Watanabe, Yoshimi Takeuchi, 1992 .

D-6-19 Power Reduction Method for On-Chip Routers Based on Packet-Position Information

Takahiro Watanabe, Kiyohisa Sato, Bai Xiujun, 2008 .

Diagnosing Fault Status in Snake-robot by Current Data

Takahiro Watanabe, Motoyasu Tanaka, Toru Asai, 2017 .

Improved delay-matching bus routing by using multi-layers

Takahiro Watanabe, Yang Tian, 2015, 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference (ICEP-IAAC).

An Efficient Algorithm for 3D NoC Architecture Optimization

Takahiro Watanabe, Xin Jiang, Ran Zhang, 2013, IPSJ Trans. Syst. LSI Des. Methodol..

Road Tunnel Ventilation Control Based on Nonlinear Programming and Fuzzy Control

Takahiro Watanabe, Masanori Shinohara, Toshihiro Koyama, 1993 .

Nonlinear Optimization Method Based on Stochastic Gradient Descent for Fast Convergence

Takahiro Watanabe, Hitoshi Iima, 2018, 2018 IEEE International Conference on Systems, Man, and Cybernetics (SMC).

Existence of a pure strategy equilibrium in finite symmetric games where payoff functions are integrally concave

Takahiro Watanabe, Takuya Iimura, 2014, Discret. Appl. Math..

Construction of fault-tolerant mesh-connected highly parallel computer and its performance analysis

Takahiro Watanabe, Katsushi Inoue, Itsuo Takanami, 1993, Systems and Computers in Japan.

A randomized algorithm for the fixed-length routing problem

Takahiro Watanabe, Ran Zhang, Tieyuan Pan, 2014, 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

On authentication between human and computer

Takahiro Watanabe, Sozo Inoue, Hiroto Yasuura, 2006, Fourth Annual IEEE International Conference on Pervasive Computing and Communications Workshops (PERCOMW'06).

Region Oriented Routing FPGA Architecture for Dynamic Power Gating

Yiping Dong, Takahiro Watanabe, Ce Li, 2012, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Visual Gesture Capture for Real-Time Interaction

Takahiro Watanabe, 이칠우, 1996 .

Fault-Tolerant Traffic-Aware Routing Algorithm for 3-D Photonic Networks-on-Chip

Takahiro Watanabe, Yu Wang, Michael Conrad Meyer, 2019, 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC).

An efficient hardware routing algorithms for NoC

Yiping Dong, Zhen Lin, Takahiro Watanabe, 2010, TENCON 2010 - 2010 IEEE Region 10 Conference.

Score Sequence Pair Problems of (r11, r12, r22)-Tournaments - - Determination of Realizability - -

Takahiro Watanabe, Takeshi Yoshimura, Masaya Takahashi, 2007, IEICE Trans. Inf. Syst..

Adaptive router with predictor using congestion degree for 3D Network-on-Chip

Takahiro Watanabe, Xin Jiang, Lian Zeng, 2013, 2013 International SoC Design Conference (ISOCC).

Real-time gesture recognition using KL expansion of image sequence

Takahiro Watanabe, Masahiko Yachida, 1997, Proceedings of the 1997 IEEE/RSJ International Conference on Intelligent Robot and Systems. Innovative Robotics for Real-World Applications. IROS '97.

Construction of an (r11, r12, r22)-Tournament from a Score Sequence Pair

Takahiro Watanabe, Takeshi Yoshimura, Masaya Takahashi, 2007, 2007 IEEE International Symposium on Circuits and Systems.

A parallel routing method for fixed pins using virtual boundary

Takahiro Watanabe, Ran Zhang, 2013, IEEE 2013 Tencon - Spring.

Triple Module Redundancy of a Laser Array Driver Circuit for Optically Reconfigurable Gate Arrays

Takahiro Watanabe, Minoru Watanabe, Minoru Watanabe, 2012, ARC.

D-6-7 A Two-Level Directory based Cache Coherence Protocol for Chip Multiprocessor

Takahiro Watanabe, Huatao Zhao, Xian Su, 2015 .

Apparatus and method for information management to facilitate searching of horizontal services

Takahiro Watanabe, Masahiro Oashi, Takayuki Hamaki, 2004 .

Erratum to: Mixed constrained image filter design using particle swarm optimization

Takahiro Watanabe, Zhiguo Bao, 2010, Artificial Life and Robotics.

Fully adaptive thermal-aware routing for runtime thermal management of 3D network-on-chip

Takahiro Watanabe, Xin Jiang, Lian Zeng, 2016, IMECS 2016.

RC-002 A Novel Low Power FPGA Architecture

Takahiro Watanabe, Yiping Done, Takahiro Watanabe, 2010 .

Analysis before Starting an Access: A New Power-Efficient Instruction Fetch Mechanism

Takahiro Watanabe, Jiongyao Ye, Yingtao Hu, 2011, IEICE Trans. Inf. Syst..

Circuit Design Using Genetic Algorithm combined with Taguchi method and Particle Swarm Optimization

Takahiro Watanabe, Zhiguo Bao, Yiwen Su, 2010 .

A fast online task placement algorithm on 3D partially reconfigurable devices

Takahiro Watanabe, Tieyuan Pan, Tingyu Zhou, 2017, TENCON 2017 - 2017 IEEE Region 10 Conference.

An Efficient Deadlock-Free Adaptive Routing Algorithm for 3D Network-on-Chips

Takahiro Watanabe, Xin Jiang, Renjie Li, 2017, 2017 IEEE 11th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC).

A Fast MER Enumeration Algorithm for Online Task Placement on Reconfigurable FPGAs

Takahiro Watanabe, Lian Zeng, Tieyuan Pan, 2016, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A Note on Reconstruction Strategies For Fault Tolerant Arrays : Minimization of the Numbers of Dangerous Processors

Takahiro Watanabe, Katsushi Inoue, Itsuo Takanami, 1993 .

High Speed -- Low Power Optical Configuration on an ORGA with a Phase-modulation Type Holographic Memory

Takahiro Watanabe, Minoru Watanabe, 2012, 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum.

A-3-1 Adaptive Routing with Congestion Estimation based on G-table

Takahiro Watanabe, Lian Zeng, Zheng Gong, 2014 .

A length matching routing method for disordered pins in PCB design

Takahiro Watanabe, Ran Zhang, Li Zhu, 2015, The 20th Asia and South Pacific Design Automation Conference.

Optimization of Power/Ground network considering area, performance and power consumption

Takahiro Watanabe, Zhiguo Bao, Donghua Wu, 2009, 2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia).

Hierarchical mask data design system (PROPHET) for aerial image simulation, automatic phase-shifter placement, and subpeak overlap checking

Takahiro Watanabe, Eiji Tsujimoto, Akemi Moniwa, 1997, Photomask and Next Generation Lithography Mask Technology.

Enhancement of hierarchical mask data design system (PROPHET)

Takahiro Watanabe, Eiji Tsujimoto, Hiroshi Fukuda, 1999, Photomask and Next Generation Lithography Mask Technology.

An adaptive routing algorithm based on network partitioning for 3D Network-on-Chip

Takahiro Watanabe, Xin Jiang, Jindun Dai, 2017, 2017 International Conference on Computer, Information and Telecommunication Systems (CITS).

Real‐time gesture recognition from dynamic images for construction of an interactive system: Application to a virtual conductor system

Takahiro Watanabe, Masahiko Yachida, Chil-Woo Lee, 1998 .

Efficient delay-matching bus routing by using multi-layers

Takahiro Watanabe, Yang Tian, Ran Zhang, 2014, 2014 International Conference on Electronics Packaging (ICEP).

Wavelength-Selective Fog-Computing Network for Big-Data Analytics of Wireless Data

Takahiro Watanabe, Yu Wang, Michael Conrad Meyer, 2019, 2019 International Conference on Electronics, Information, and Communication (ICEIC).

Sorting-Based I/O Connection Assignment and Non-Manhattan RDL Routing for Flip-Chip Designs

Takahiro Watanabe, Ran Zhang, 2015 .

Adaptive Look Ahead algorithm for 2-D mesh NoC

Takahiro Watanabe, Xin Jiang, Lian Zeng, 2015, 2015 IEEE International Advance Computing Conference (IACC).

Low Power and High Speed Network on Chip Architecture for BP Neural Network

Yiping Dong, Takahiro Watanabe, Yang Wang, 2009 .

5-Axis control machining based on solid model.

Takahiro Watanabe, Yoshimi Takeuchi, Hiroyuki Shimizu, 1990 .

PDA-HyPAR: Path-diversity-aware hybrid planar adaptive routing algorithm for 3D NoCs

Takahiro Watanabe, Xin Jiang, Renjie Li, 2018, 2018 19th International Symposium on Quality Electronic Design (ISQED).

A sorting-based micro-bump assignment for 3D ICs

Takahiro Watanabe, Tieyuan Pan, Ran Zhang, 2015, 2015 International SoC Design Conference (ISOCC).

Pure strategy equilibrium in finite weakly unilaterally competitive games

Takahiro Watanabe, Takuya Iimura, 2016, Int. J. Game Theory.

2P1-C06 Evaluation of Impedance Adjustment Function of Human Lower Limb Using Pedaling Exercise : Second Report : Evaluation for an Endpoint Trajectory Prediction during Pedaling Exercises(Sense, Motion and Measurement (3))

Takahiro Watanabe, Satoshi Tadokoro, Masashi Konyo, 2012 .

Osaka urban phased array radar network experiment

Takahiro Watanabe, Nobuhiro Takahashi, Hiroshi Kikuchi, 2017, 2017 IEEE International Geoscience and Remote Sensing Symposium (IGARSS).

High dependable implementation of Neural Networks with networks on chip architecture and a backtracking routing algorithm

Yiping Dong, Zhen Lin, Takahiro Watanabe, 2009, 2009 Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia).

Mixed constrained image filter design using particle swarm optimization

Takahiro Watanabe, Zhiguo Bao, 2010, Artificial Life and Robotics.

Automatic parallel optical proximity correction and verification system

Takahiro Watanabe, Eiji Tsujimoto, Keiji Maeda, 2000, Advanced Lithography.

High performance implementation of Neural Networks by networks on chip with 5-port 2-virtual channels

Yiping Dong, Zhen Lin, Takahiro Watanabe, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

A Low-power Shared Cache Design with Modified PID Controller for Efficient Multicore Embedded Systems

Takahiro Watanabe, Huatao Zhao, Jiongyao Ye, 2019, J. Inf. Process..

Flexible L1 cache optimization for a low power embedded system

Takahiro Watanabe, Sijie Yin, Yuxin Sun, 2013, Proceedings 2013 International Conference on Mechatronic Sciences, Electric Engineering and Computer (MEC).

Real-time gesture recognition using eigenspace from multi-input imagesequences

Takahiro Watanabe, Masahiko Yachida, 1999, Systems and Computers in Japan.

A sorting-based IO connection assignment for flip-chip designs

Takahiro Watanabe, Ran Zhang, Xue Wei, 2013, 2013 IEEE 10th International Conference on ASIC.

An Online Task Placement Algorithm Based on MER Enumeration for Partially Reconfigurable Device

Takahiro Watanabe, Li Zhu, Lian Zeng, 2015, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Multiple Network-on-Chip Model for High Performance Neural Network

Yiping Dong, Zhen Lin, Takahiro Watanabe, 2010 .

FLOOR-PLAN DESIGN SYSTEM FOR LSI LAYOUT.

Takahiro Watanabe, Hiroshi Baba, 1985 .

A fine grain cooled logic architecture for low-power processors

Takahiro Watanabe, Tadao Nakamura, Hiroyuki Matsubara, 2001 .

A hierarchical MCM routing using four-via routing

Takahiro Watanabe, T. Fujii, 1996, Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems.

Region-Oriented Placement Algorithm for Coarse-Grained Power-Gating FPGA Architecture

Yiping Dong, Takahiro Watanabe, Ce Li, 2012, IEICE Trans. Inf. Syst..

RC-008 Rapid Design of a Multiprocessor System for a JPEG Decoder on FPGA

Takahiro Watanabe, Keyan Chen, Dawei Cao, 2008 .

A Behavior-based Adaptive Access-mode for Low-power Set-associative Caches in Embedded Systems

Takahiro Watanabe, Jiongyao Ye, Yingtao Hu, 2012, J. Inf. Process..

An Adaptive Various-Width Data Cache for Low Power Design

Takahiro Watanabe, Yu Wan, Jiongyao Ye, 2011, IEICE Trans. Inf. Syst..

An efficient design algorithm for exploring flexible topologies in custom adaptive 3D NoCs for high performance and low power

Takahiro Watanabe, Xin Jiang, Ran Zhang, 2011, 2011 9th IEEE International Conference on ASIC.

A Time-based Leakage-aware Algorithm for Task Placement and Scheduling Problem on Dynamic Reconfigurable FPGA

Takahiro Watanabe, Tieyuan Pan, Zhiguo Bao, 2018, 2018 5th International Conference on Systems and Informatics (ICSAI).

A behavior-based reconfigurable cache for the low-power embedded processor

Takahiro Watanabe, Jiongyao Ye, Jiannan Jin, 2011, 2011 9th IEEE International Conference on ASIC.

High Performance Fully Adaptive Runtime Thermal-Aware Routing Algorithm for 3D NoC

Takahiro Watanabe, Xin Jiang, Lian Zeng, 2016, IMECS 2016.

INDOOR, COMPACT, AND SMART CONTROL HIGH SPEED OPTICAL WIRELESS COMMUNICATIONS

Takahiro Watanabe, Toshihiro Kato, Koji Nonaka, 2006 .

Efficient simulated annealing-based placement algorithm for Island style FPGAs

Takahiro Watanabe, Lan Ma, Runxiao Shi, 2018 .

0.18μm process Optically Reconfigurable Gate Array VLSI

Takahiro Watanabe, Minoru Watanabe, 2012 .

Sealed Bid Mulit-object Auctions with Necessary Bundles and Its Application to Spectrum Auctions

Takahiro Watanabe, Tomomi Matsui, Takahiro Watanabe, 2001, PRIMA.

A-3-2 Adaptive Router with Predictor using Congestion Degree

Takahiro Watanabe, Lian Zeng, 2013 .

Layer Assignment and Equal-length Routing for Disordered Pins in PCB Design

Takahiro Watanabe, Ran Zhang, Li Zhu, 2015, IPSJ Trans. Syst. LSI Des. Methodol..

Hybrid path-diversity-dominant output selection method for Network-on-Chip systems

Takahiro Watanabe, Xin Jiang, Jindun Dai, 2017, 2017 International SoC Design Conference (ISOCC).

Realizability of Score Sequence Pair of an (r1l, r12, r22)-Tournament

Takahiro Watanabe, Takeshi Yoshimura, Masaya Takahashi, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

A Variable Bitline Data Cache for low power design

Takahiro Watanabe, Jiongyao Ye, 2010, 2010 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia).

A novel genetic algorithm with different structure selection for circuit design optimization

Takahiro Watanabe, Zhiguo Bao, 2009, Artificial Life and Robotics.

Mixed Constrained Image Filter Design for Salt-and-Pepper Noise Reduction Using Genetic Algorithm

Takahiro Watanabe, Xiaoming Zhao, Zhiguo Bao, 2011 .

Dependable Optically Reconfigurable Gate Array with a Phase-Modulation Type Holographic Memory

Takahiro Watanabe, Minoru Watanabe, 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

Global router for analog function blocks based on the branch-and-bound algorithm

Takahiro Watanabe, Masahiro Kawakita, Tadanao Tsubota, 1995 .

A Hotspot-Pattern-Aware Routing Algorithm for Networks-on-Chip

Takahiro Watanabe, Xin Jiang, Michael Conrad Meyer, 2019, 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC).

Low Power Placement and Routing for the Coarse-Grained Power Gating FPGA Architecture

Yiping Dong, Takahiro Watanabe, Ce Li, 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Facial Expression Recognition and its Degree Estimation for Man-Machine Interface

Takahiro Watanabe, Masahiko Yachida, Satoshi Kimura, 1998 .

A Sophisticated Routing Algorithm in 3D NoC with Fixed TSVs for Low Energy and Latency

Takahiro Watanabe, Xin Jiang, Lian Zeng, 2014, IPSJ Trans. Syst. LSI Des. Methodol..

Real time recognition of gesture and gesture degree information using multi input image sequences

Takahiro Watanabe, Masahiko Yachida, 1998, Proceedings. Fourteenth International Conference on Pattern Recognition (Cat. No.98EX170).

Automatic parallel optical proximity correction system for application with hierarchical data structure

Takahiro Watanabe, Eiji Tsujimoto, Kyoji Nakajo, 1999, Advanced Lithography.

D-6-10 Adaptive Look Ahead Routing Algorithm for 2-D mesh Topology

Takahiro Watanabe, Lian Zeng, Abhilash Menon, 2015 .

Recognition of complicated gesture in real-time interactive system

Takahiro Watanabe, Masahiko Yachida, Chil-Woo Lee, 1996, Proceedings 5th IEEE International Workshop on Robot and Human Communication. RO-MAN'96 TSUKUBA.

Fault tolerance of a holographic storage system

Takahiro Watanabe, Minoru Watanabe, 2010, 2010 10th International Symposium on Communications and Information Technologies.

A performance enhanced dual-switch Network-on-Chip architecture

Takahiro Watanabe, Lian Zeng, 2015, ASP-DAC.

A Traffic-Robust Routing Algorithm for Network-on-Chip Systems

Takahiro Watanabe, Xin Jiang, Michael Conrad Meyer, 2019, 2019 IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC).

An efficient 3D NoC synthesis by using genetic algorithms

Takahiro Watanabe, Xin Jiang, 2010, TENCON 2010 - 2010 IEEE Region 10 Conference.

A hybrid layer-multiplexing and pipeline architecture for efficient FPGA-based multilayer neural network

Yiping Dong, Zhen Lin, Takahiro Watanabe, 2011 .

Binary action games: Deviation properties, semi-strict equilibria and potentials

Takahiro Watanabe, Takuya Iimura, Pierre von Mouche, 2018, Discret. Appl. Math..

A-1-33 A Time-efficient Approach to Evolve GA-based Image Filters

Takahiro Watanabe, Endong Ni, 2012 .