S. Vanhaelemeersch

A 0.314/spl mu/m/sup 2/ 6T-SRAM cell build with tall triple-gate devices for 45nm applications using 0.75NA 193nm lithography

R. Rooyackers, M. Van Hove, K. Ronse, 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

A Novel Deep Trench Isolation Featuring Airgaps for a High-Speed 0.13μm SiGe:C BiCMOS Technology

S. Decoutere, S. Van Huylenbroeck, P. Leray, 2006, 2006 International Symposium on VLSI Technology, Systems, and Applications.

Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274/spl mu/m/sup 2/ 6T-SRAM cell and advanced CMOS logic circuits

R. Rooyackers, M. Van Hove, K. Ronse, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Full-field EUV and immersion lithography integration in 0.186μm2 FinFET 6T-SRAM cell

B. Parvais, R. Rooyackers, K. Ronse, 2008, 2008 IEEE International Electron Devices Meeting.

High Q inductor add-on module in thick Cu/SiLK/sup TM/ single damascene

S. Decoutere, B. Nauwelaers, S. Jenei, 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

Post-Etch Cleaning after Dry Etching the Emitter Windows to Improve the Bipolar Characteristics in a 0.5μm BiCMOS Process

S. Decoutere, L. Deferm, F. Vleugels, 1994, ESSDERC '94: 24th European Solid State Device Research Conference.