K. Yahashi

Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory

Y. Iwata, A. Nitayama, H. Tanaka, 2007, 2007 IEEE Symposium on VLSI Technology.

Fin-Array-FET on bulk silicon for sub-100 nm trench capacitor DRAM

K. Yahashi, R. Katsumata, M. Morikado, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

High-density and high-speed 128Mb chain FeRAM™ with SDRAM-compatible DDR2 interface

S. Shiratake, A. Nitayama, K. Yahashi, 2006, 2009 Symposium on VLSI Technology.

A High Performance pMOSFET with Two-step Recessed SiGe-S/D Structure for 32nm node and Beyond

K. Yahashi, N. Kusunoki, K. Ohuchi, 2006, 2006 European Solid-State Device Research Conference.

Scalable eSiGe S/D Technology with Less Layout Dependence for 45-nm Generation

S. Fujita, F. Matsuoka, T. Sanuki, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

High Density and High Reliability Chain FeRAM with Damage-Robust MOCVD-PZT Capacitor with SrRuO3/IrO2 Top Electrode for 64Mb and Beyond

S. Shiratake, A. Nitayama, K. Yahashi, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length

K. Yahashi, H. Ishiuchi, N. Aoki, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm finfet with elevated source/drain extension

K. Yahashi, H. Ishiuchi, N. Aoki, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..