Sebastien Haendler

发表

Circuit-Level Modeling of SRAM Minimum Operating Voltage Vddmin in the C40 Node

Nicolas Planes, Amit Chhabra, Lorenzo Ciampolini, 2012 .

Process Architecture for Spatial and Temporal Variability Improvement of SRAM Circuits at the 45nm Node

O. Menut, C. Laviron, J. Bonnouvrier, 2008 .

Impact of a 10nm Ultra-Thin BOX (UTBOX) and Ground Plane on FDSOI devices for 32nm node and below

C. Laviron, Claire Fenouillet-Beranger, Stephane Denorme, 2009, ESSDERC 2009.

Performance analysis of multi-VT design solutions in 28nm UTBB FD-SOI technology

Bertrand Pelloux-Prayer, Alexandre Valentian, Philippe Flatresse, 2013, 2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Impact of dynamic variability on the operation of CMOS inverter

Gerard Ghibaudo, Sebastien Haendler, Charalabos A. Dimitriadis, 2013 .

Characterization and modeling of low frequency noise in CMOS inverters

Sebastien Haendler, Charalabos A. Dimitriadis, Gerard Ghibaudo, 2013 .

Impact of low-frequency noise variability on statistical parameter extraction in ultra-scaled CMOS devices

Gerard Ghibaudo, Sebastien Haendler, Charalabos A. Dimitriadis, 2014 .

Is SOI CMOS A Promising Technology For SOCs In High Frequency Range

Romain Gwoziecki, Alain Chantre, Daniel Gloria, 2005 .

Full gate voltage range Lambert-function based methodology for FDSOI MOSFET parameter extraction

Sebastien Haendler, T. A. Karatsori, Charalabos A. Dimitriadis, 2015 .

Design-in reliability approach for Hot Carrier injection modeling in the context of AMS/RF applications

Vincent Huard, Thomas Quemerais, Laurence Moquillon, 2011, 2011 International Reliability Physics Symposium.

Sub-threshold 10T SRAM bit cell with read/write XY selection

Bruno Allard, Fady Abouzeid, Sebastien Haendler, 2015 .

Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control

Jean-Philippe Noel, Vivek Asthana, Malathi Kar, 2013, 2013 Proceedings of the ESSCIRC (ESSCIRC).

Evolution of low frequency noise and noise variability through CMOS bulk technology nodes

Gerard Ghibaudo, J. Rosa, Sebastien Haendler, 2013 .

Thorough Investigation of Kink-Related Excess Noise in Deep Submicron SOI N-MOSFETs on Unibond Substrate

Sebastien Haendler, J. L. Pelloie, C. Raynaud, 1999 .

Sebastien Haendler, Jalal Jomaah, Christine Raynaud, 2000 .

65nm Low Power (LP) SOI Technology on High Resistivity (HR) Substrate for WLAN and Mmwave SOCs

Baudouin Martineau, Frederic Gianesello, Georges Guegan, 2009 .

Drain-Current Flicker Noise Modeling in nMOSFETs From a 14-nm FDSOI Technology

Gerard Ghibaudo, Sebastien Haendler, Eleftherios G. Ioannidis, 2015, IEEE Transactions on Electron Devices.

SOI Technologies Overview for Low-Power Low-Voltage Radio-Frequency Applications

O. Rozeau, Sebastien Haendler, J. Boussey, 2000 .

Characterization and modeling of drain current local variability in 28 and 14 nm FDSOI nMOSFETs

Gerard Ghibaudo, Sebastien Haendler, Nicolas Planes, 2016 .