Ren-Der Chen

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A Low-Power Architecture for the Design of a One-Dimensional Median Filter

Chun-Hsien Yeh, Pei-Yin Chen, Ren-Der Chen, 2015, IEEE Transactions on Circuits and Systems II: Express Briefs.

An efficient method for the decomposition and resynthesis of speed-independent circuits

Jer Min Jou, Ren-Der Chen, Yeu-Horng Shiau, 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

Design of a Transparent Pipeline-Based Multiplier

Ren-Der Chen, Xiang Chih Kuo, 2016 .

Hazard-free synthesis and decomposition of asynchronous circuits

Jer-Min Jou, Ren-Der Chen, Yeu-Horng Shiau, 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

Investigating the FIFO design styles based on the Balsa synthesis system

Ren-Der Chen, Che-An Lee, Pei-Hua Hsieh, 2011, 2011 International Symposium on Integrated Circuits.

Design of a dynamic pipelined architecture for fuzzy color correction

Shiann-Rong Kuang, Jer-Min Jou, Ren-Der Chen, 2002, IEEE Trans. Very Large Scale Integr. Syst..

Design of an Area-Efficient One-Dimensional Median Filter

Chun-Hsien Yeh, Pei-Yin Chen, Ren-Der Chen, 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

Hardware Implementation for a Genetic Algorithm

Leang-San Shieh, Heidar A. Malki, Yu-Pin Chang, 2008, IEEE Transactions on Instrumentation and Measurement.

A Study on the Performance Characteristics of a Synchronous Elastic FIR Filter

Ren-Der Chen, Sheng Yu Kao, 2016 .

Comparative design of floating-point arithmetic units using the Balsa synthesis system

Ren-Der Chen, Wan-Chen Liu, Yu-Cheng Chou, 2011, 2011 International Symposium on Integrated Circuits.

Clique partitioning based integrated architecture synthesis for VLSI chips

Shiann-Rong Kuang, Jer Min Jou, Ren-Der Chen, 1993, 1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers.

A super fast and memory efficient diagnostic simulation algorithm for combinational circuits

Shung-Chih Chen, Jer-Min Jou, Ren-Der Chen, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

Design of low-error fixed-width multipliers for DSP applications

Jer Min Jou, Shiann Rong Kuang, Ren-Der Chen, 1999 .

An integrated synthesis system for speed-independent asynchronous circuits

Jer Min Jou, Ren-Der Chen, Ke-Ming Lin, 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

A new efficient fuzzy algorithm for color correction

Jer Min Jou, Shiann Rong Kuang, Ren-Der Chen, 1999 .

Multiport memory based data path allocation focusing on interconnection optimization

Shiann-Rong Kuang, Jer-Min Jou, Ren-Der Chen, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

An index coding algorithm for image vector quantization

Pei-Yin Chen, Ren-Der Chen, 2003, IEEE Trans. Consumer Electron..

An efficient method for the decomposition and resynthesis of speed-independent circuits

Jer Min Jou, Ren-Der Chen, 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).

Design of a Transparent Pipeline Based on Synchronous Elastic Circuits

Ren-Der Chen, Sheng Hung Chang, 2013 .

A High-Performance Bidirectional Architecture for the Quasi-Comparison-Free Sorting Algorithm

Wei-Ting Chen, Pei-Yin Chen, Ren-Der Chen, 2021, IEEE Transactions on Circuits and Systems I: Regular Papers.