G. M. Blair

发表

CMOS buffer tapering with interconnect capacitances

G. M. Blair, 1996 .

Professional skills for first-year engineering students

G. M. Blair, C. M. Robinson, 1995 .

Designing low-power digital CMOS

G. M. Blair, 1994 .

A review of the discrete Fourier transform. 1. Manipulating the powers of two

G. M. Blair, 1995 .

Skew-free clock distribution for standard-cell VLSI designs

G. M. Blair, 1992 .

Laying the foundations for effective teamwork

G. M. Blair, 1993 .

Verilog: accelerating digital design

G. M. Blair, 1997 .

A review of the discrete Fourier transform. 2. Non-radix algorithms, real transforms and noise

G. M. Blair, 1995 .

Presentation skills for emergent managers

G. M. Blair, 1991 .

PLA design for single-clock CMOS

G. M. Blair, G. Blair, 1992 .

Self-generating clock using an augmented distribution network

G. M. Blair, 1997 .

Comments on "New single-clock CMOS latches and flip-flops with improved speed and power savings"

G. M. Blair, 1997 .

Content addressability: an exercise in the semantic matching of hardware and software design

G. M. Blair, P. B. Denyer, 1989 .

Comments on "A robust single phase clocking for low power, high-speed VLSI applications" [and reply]

G. M. Blair, 1996 .

Groups that work (management)

G. M. Blair, 1991 .

Low cost sorting circuit for VLSI

G. M. Blair, 1996 .

Comment on new differential flip-flops from Yuan and Svensson

G. M. Blair, 1996 .

Viterbi Equalization: low-power VLSI module design

Bernie Mulgrew, G. M. Blair, J. M. Dobson, 1996 .

A simple digital circuit for the Towers of Hanoi problem

G. M. Blair, 1997 .

Circuit improvements for high-speed domino logic: for the Manchester carry chain

G. M. Blair, 1998 .

How to write right

G. M. Blair, 1992 .

A content addressable memory with a fault-tolerance mechanism

G. M. Blair, 1987 .

Two-dimensional micropipelines: for parallel-to-serial data conversion

G. M. Blair, G. S. Taylor, 1998 .

Design for the discrete cosine transform in VLSI

G. M. Blair, G. S. Taylor, 1998 .

The equivalence of twos-complement addition and the conversion of redundant-binary to twos-complement numbers

G. M. Blair, 1998 .

Fast two's complement VLSI adder design

G. M. Blair, J. M. Dobson, 1995 .