Ming-Chien Tsai

Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array

Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, 2012, Proceedings of Technical Program of 2012 VLSI Design, Automation and Test.

Asymmetrical Write-assist for single-ended SRAM operation

Ming-Chien Tsai, Ming-Hsien Tu, Shyh-Jye Jou, 2009, 2009 IEEE International SOC Conference (SOCC).

Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM

Ming-Chien Tsai, Yi-Wei Lin, Wei-Chiang Shih, 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems.

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

Chien-Yu Lu, Ming-Chien Tsai, Ming-Hsien Tu, 2012, IEEE Journal of Solid-State Circuits.

An All-Digital High-Precision Built-In Delay Time Measurement Circuit

Ming-Chien Tsai, Ching-Hwa Cheng, Chiou-Mao Yang, 2008, 26th IEEE VLSI Test Symposium (vts 2008).

A full-synthesizable high-precision built-in delay time measurement circuit

Ming-Chien Tsai, Ching-Hwa Cheng, Ching-Hwa Cheng, 2009, 2009 Asia and South Pacific Design Automation Conference.

An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array

Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, 2012, Proceedings of Technical Program of 2012 VLSI Design, Automation and Test.

An all-digital bit transistor characterization scheme for CMOS 6T SRAM array

Ming-Chien Tsai, Yi-Wei Lin, Wei-Chiang Shih, 2012, 2012 IEEE International Symposium on Circuits and Systems.

High-Performance Low-Power Full-Swing Full Adder Cores with Output Driving Capability

Ming-Chien Tsai, Yu-Cherng Hung, Shao-Hui Shieh, 2006, APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems.

Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist

Ming-Chien Tsai, Ming-Hsien Tu, Shyh-Jye Jou, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.