Shyh-Jye Jou

发表

Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array

Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, 2012, Proceedings of Technical Program of 2012 VLSI Design, Automation and Test.

All-Digital Synchronization for SC/OFDM Mode of IEEE 802.15.3c and IEEE 802.11ad

Wei-Chang Liu, Shyh-Jye Jou, Ting-Chen Wei, 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

Simultaneous switching noise analysis and low-bounce buffer design

Wei-Chung Cheng, Shyh-Jye Jou, Yu-Tao Lin, 1998 .

desire to reduce (or eliminate) complex and in P1149.4 Environment

Shyh-Jye Jou, Chauchin Su, Yue-Tsang Chen, 1997 .

Design techniques for high-speed multirate multistage FIR digital filters

Shyh-Jye Jou, M.-C. Lin, H.-Y. Chen, 2006 .

Fixed-width multiplier for DSP application

Shyh-Jye Jou, Hui-Hsuan Wang, 2000, Proceedings 2000 International Conference on Computer Design.

Digital Self-Interference Cancellation for OFDM Full-Duplex Transmission in 60 GHz Band

Shyh-Jye Jou, Hsun-Wei Chan, Henry Lopez Davila, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist

Hao-I Yang, Ming-Hsien Tu, Nan-Chun Lien, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

Welcome from the general chairs

Shyh-Jye Jou, C. Patrick Yue, Michel Brillouët, 2012, VLSI-DAT.

Error-resilient sequential cells with successive time borrowing for stochastic computing

Wei-Chang Liu, Shyh-Jye Jou, Chia-Hsiang Yang, 2016, 2016 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

Multi-gigabit serial link transmitter - off-chip and on-chip

Shyh-Jye Jou, Chih-Hsien Lin, Chih-Ning Chen, 2005, Conference, Emerging Information Technology 2005..

Low-power self-timed circuit design technique

Shyh-Jye Jou, I-Yao Chung, 1997 .

Spatial-cue-based multi-band binaural noise reduction for hearing aids

Shyh-Jye Jou, Cheng-Yen Yang, Chih-Wei Liu, 2013, SiPS 2013 Proceedings.

0.5 VDD digitally controlled oscillators design with compensation techniques for PVT variations

Shyh-Jye Jou, Yuan-Hua Chu, Chia-Wen Chang, 2011, 2011 9th IEEE International Conference on ASIC.

Residual sampling clocking offset estimation and compensation for FBMC-OQAM baseband receiver in the 60 GHz band

Shyh-Jye Jou, Henry Lopez Davila, Chun-Yi Liu, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

Metrology for analog module testing using analog testability bus

Shyh-Jye Jou, Yue-Tsang Chen, Chanchin Su, 1996, ICCAD 1996.

Asymmetrical Write-assist for single-ended SRAM operation

Ming-Chien Tsai, Ming-Hsien Tu, Shyh-Jye Jou, 2009, 2009 IEEE International SOC Conference (SOCC).

The Mixed-Mode Interface

A. Richard Newton, Shyh-Jye Jou, Resve Saleh, 1994 .

On chip voltage down converter for LV/LP digital system

Shyh-Jye Jou, Tsu-Lin Chen, 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

A Systematic ANSI S1.11 Filter Bank Specification Relaxation and Its Efficient Multirate Architecture for Hearing-Aid Systems

Shyh-Jye Jou, Cheng-Yen Yang, Chih-Wei Liu, 2016, IEEE/ACM Transactions on Audio, Speech, and Language Processing.

A well-structured modified Booth multiplier design

Shyh-Jye Jou, Li-Rong Wang, Chung-Len Lee, 2008, 2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A 40 nm 0.32 V 3.5 MHz 11T single-ended bit-interleaving subthreshold SRAM with data-aware write-assist

Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang, 2013, International Symposium on Low Power Electronics and Design (ISLPED).

QAM/VSB dual mode equalizer design and implementation

Shyh-Jye Jou, C. C. Huang, C. F. Wu, 1999, AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360).

Low-voltage Low-power If-baseband Digital Down Converter

Shyh-Jye Jou, Tsan-I Hsu, C. K. Wang, 1997, Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications.

A 40nm 256kb 6T SRAM with threshold power-gating, low-swing global read bit-line, and charge-sharing write with Vtrip-tracking and negative source-line write-assists

Chien-Yu Lu, Ming-Hsien Tu, Kuen-Di Lee, 2014, 2014 27th IEEE International System-on-Chip Conference (SOCC).

A serial link transceiver for USB2 high-speed mode

Shyh-Jye Jou, Tim Liu, Chien-Hsiung Lee, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Golay-Correlator Window-Based Noise Cancellation Equalization Technique for 60-GHz Wireless OFDM/SC Receiver

Wei-Chang Liu, Shyh-Jye Jou, Chun-Yi Liu, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A low-power Mandarin-specific hearing aid chip

Ming-Hsien Tu, Shyh-Jye Jou, Chih-Wei Liu, 2010, 2010 IEEE Asian Solid-State Circuits Conference.

Low Complexity Formant Estimation Adaptive Feedback Cancellation for Hearing Aids Using Pitch Based Processing

Shyh-Jye Jou, Tian-Sheuan Chang, Yu-Wen Lin, 2014, IEEE/ACM Transactions on Audio, Speech, and Language Processing.

A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist

Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

A 80-uW 2-Mb/s transceiver for human body channel binaural communication

Tzu-Hsien Sang, Shyh-Jye Jou, Yi-Hung Shen, 2012, 2012 IEEE Biomedical Circuits and Systems Conference (BioCAS).

8T Single-ended sub-threshold SRAM with cross-point data-aware write operation

Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

Sub $\mu$ W Noise Reduction for CIC Hearing Aids

Shyh-Jye Jou, Tian-Sheuan Chang, Cheng-Wen Wei, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

DESIGN AND TESTING OF A MIXED SIGNAL MATCHED FILTER FOR IS-95 CDMA CODE ACQUISITION

Shyh-Jye Jou, C.-C. Su, H.-C. Lin, 1998 .

A 28nm 36kb high speed 6T SRAM with source follower PMOS read and bit-line under-drive

Shyh-Jye Jou, Yi-Wei Chiu, Chi-Hao Hong, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Dynamic Error-Compensated Fixed-Width Booth Multiplier Based on Conditional-Probability of Input Series

Shyh-Jye Jou, Yuan-Ho Chen, Wen-Quan He, 2016, Circuits Syst. Signal Process..

Multi-Gigabit Pre-Emphasis Design and Analysis for Serial Link

Shyh-Jye Jou, Chih-Hsien Lin, Chih-Ning Chen, 2005, IEICE Trans. Electron..

A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design

Shyh-Jye Jou, Li-Rong Wang, Kai-Yu Lo, 2013, IEICE Trans. Electron..

Neuromorphic Pitch Based Noise Reduction for Monosyllable Hearing Aid System Application

Shyh-Jye Jou, Yi-Cheng Huang, Yu-Jui Chen, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

Low Computational Complexity Pitch Based VAD for Dynamic Environment in Hearing Aids

Shyh-Jye Jou, Yu-Jui Chen, Cheng-Wen Wei, 2010, BIOSIGNALS 2010.

Simultaneous switching noise analysis and low bouncing buffer design [CMOS ICs]

Wei-Chung Cheng, Shyh-Jye Jou, Yu-Tao Lin, 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

EMOTA : an event-driven MOS timing simulator for VLSI circuits

Shyh-Jye Jou, Wen-Zen Shen, Y.-S. Tao, 1990 .

Design and implementation of dynamic Word-Line pulse write margin monitor for SRAM

Ming-Chien Tsai, Yi-Wei Lin, Wei-Chiang Shih, 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems.

Testing strategies for a 9T sub-threshold SRAM

Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang, 2012, 2012 IEEE International Test Conference.

60GHz FBMC 基頻接收器之符元間干擾與載波間干擾抑制等化器

Shyh-Jye Jou, Edmund Wen Jen Leong, 周世傑, 2015 .

A 50 Gb/s Adaptive ADFE with SNR Based Power Management for 2-PAM Systems

Shyh-Jye Jou, Yu-Chun Lin, Chee-Kit Ng, 2019, 2019 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

Chien-Yu Lu, Ming-Chien Tsai, Ming-Hsien Tu, 2012, IEEE Journal of Solid-State Circuits.

A MMSE Joint Feedback Feed-forward Equalizer for FBMC-OQAM Baseband Receiver in the 60 GHz Band

Shyh-Jye Jou, Chang-Ting Wu, Chun-Yi Liu, 2017, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

A low-power charge sharing hierarchical bitline and voltage-latched sense amplifier for SRAM macro in 28 nm CMOS technology

Shyh-Jye Jou, Yi-Wei Chiu, Chi-Hao Hong, 2014, 2014 27th IEEE International System-on-Chip Conference (SOCC).

4/2 PAM serial link transmitter with tunable pre-emphasis

Shyh-Jye Jou, Chih-Hsien Lin, Chih-Ning Chen, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

Design of a Multimode QC-LDPC Decoder Based on Shift-Routing Network

Shyh-Jye Jou, Hsie-Chia Chang, Chen-Yi Lee, 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

Perceptual multiband spectral subtraction for noise reduction in hearing aids

Shyh-Jye Jou, Tian-Sheuan Chang, Cheng-Wen Wei, 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

On-chip voltage down converter for low-power digital system

Shyh-Jye Jou, Tsu-Lin Chen, 1998 .

Mixed-Mode Simulation and Implementation

A. Richard Newton, Shyh-Jye Jou, Resve Saleh, 1994 .

50Gb/s 115mW 全數位適應性決策回授等化器與雜訊抑制濾波器

Shyh-Jye Jou, 周世傑, Chee-Kit Ng, 2013 .

Mixed-VTH (MVT) CMOS circuit design for low power cell libraries

Shyh-Jye Jou, Chia-Lin Hu, Jiun-Yi Lin, 2007, 2007 IEEE International SOC Conference.

Continuous-flow Parallel Bit-Reversal Circuit for MDF and MDC FFT Architectures

Shyh-Jye Jou, Sau-Gee Chen, Mario Garrido, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

Low switching noise and load-adaptive output buffer design techniques

Shyh-Jye Jou, Shu-Hua Kuo, Jui-Ta Chiu, 2001 .

High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder

Yi-Wei Lin, Hao-I Yang, Wei-Chiang Shih, 2012, 2012 IEEE International Symposium on Circuits and Systems.

An I/sub DDQ/ based built-in concurrent test technique for interconnects in a boundary scan environment

Shyh-Jye Jou, Chauchin Su, Kychin Hwang, 1994, Proceedings., International Test Conference.

A 6Gbps Serial Link Transmitter with Pre-emphasis

Shyh-Jye Jou, Chih-Hsien Lin, Chung-Hong Wang, 2007, 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A Low-Overhead Interference Canceller for High-Mobility STBC-OFDM Systems

Shyh-Jye Jou, Hsiao-Yun Chen, Wei-Kai Chang, 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

Low-Power Embedded DSP Core for Communication Systems

Shyh-Jye Jou, Wei-Hao Chen, Ya-Lan Tsao, 2003, EURASIP J. Adv. Signal Process..

Circuits design optimization using symbolic approach

Shyh-Jye Jou, Chauchin Su, Kou-Fong Liu, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

2.5 Gbps CMOS laser diode driver with APC and digitally controlled current modulation

Shyh-Jye Jou, Chih-Hsien Lin, Chun-Cheng Kuo, 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.

Hardware nested looping of parameterized and embedded DSP core

Shyh-Jye Jou, Wei-Hao Chen, Wen-Sheng Cheng, 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

Subthreshold SRAM macro design with pulse-controlled dynamic voltage scaling (PC-DVS)

Shyh-Jye Jou, Yuan-Hua Chu, Jun-Kai Zhao, 2014, 2014 International SoC Design Conference (ISOCC).

A 12.5 Gbps CMOS input sampler for serial link receiver front end

Shyh-Jye Jou, Chih-Hsien Lin, Yen-I Wang, 2005, 2005 IEEE International Symposium on Circuits and Systems.

An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications

Shyh-Jye Jou, Hsie-Chia Chang, Chen-Yi Lee, 2008, IEEE Journal of Solid-State Circuits.

An ultra-low voltage hearing aid chip using variable-latency design technique

Shyh-Jye Jou, Chih-Wei Liu, Kuo-Chiang Chang, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Novel FFT processor with parallel-in-parallel-out in normal order

Shyh-Jye Jou, Hsiao-Yun Chen, Hsiang-Sheng Hu, 2009, 2009 International Symposium on VLSI Design, Automation and Test.

Design and implementation of synchronization detection for IEEE 802.15.3c

Wei-Chang Liu, Shyh-Jye Jou, Ya-Shiue Huang, 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test.

Parallel scrambler for high-speed applications

Shyh-Jye Jou, Chih-Hsien Lin, Chih-Ning Chen, 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

Digitally-controlled cell-based oscillator with multi-phase differential outputs

Shyh-Jye Jou, Ming-Chiuan Su, 2011, 2011 9th IEEE International Conference on ASIC.

Correction to "Low complexity formant estimation adaptive feedback cancellation for hearing aids using pitch based processing"

Shyh-Jye Jou, Tian-Sheuan Chang, Yu-Wen Lin, 2014, TASLP.

Blind Mode/GI Detection and Coarse Symbol Synchronization for DVB-T/H

Wei-Chang Liu, Shyh-Jye Jou, Ting-Chen Wei, 2007, 2007 IEEE International Symposium on Circuits and Systems.

A pipelined multiplier-accumulator using a high-speed, low-power static and dynamic full adder design

Shyh-Jye Jou, Chauchin Su, Chang-Yu Chen, 1995 .

A Low-Jitter Cell-Based Digitally Controlled Oscillator With Differential Multiphase Outputs

Shyh-Jye Jou, Wei-Zen Chen, Ming-Chiuan Su, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

On-Chip Voltage Dowin Converter for LVLP Digital System

Shyh-Jye Jou, Tsu-Lin Chen, 1997 .

Module generator of data recovery for serial link receiver

Shyh-Jye Jou, Yen-Hung Chen, Chih-Hsien Lin, 2003, IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings..

A pseudo MMSE linear equalizer for 60GHz single carrier baseband receiver

Shyh-Jye Jou, Hsun-Wei Chan, Chang-Ting Wu, 2017, 2017 IEEE 12th International Conference on ASIC (ASICON).

STBC-OFDM Downlink Baseband Receiver for Mobile WMAN

Shyh-Jye Jou, Hsiao-Yun Chen, Hsiang-Sheng Hu, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

10Gbps decision feedback equalizer with dynamic lookahead decision loop

Shyh-Jye Jou, Muh-Tian Shiue, Yu-Chun Lin, 2009, 2009 IEEE International Symposium on Circuits and Systems.

Full-digital high throughput design of adaptive decision feedback equalizers using coefficient-lookahead

Shyh-Jye Jou, Yu-Chun Lin, Wen-Quan He, 2015, 2015 IEEE 11th International Conference on ASIC (ASICON).

A 28mW OFDM baseband receiver chip for DVB-T/H with all digital synchronization

Wei-Chang Liu, Shyh-Jye Jou, Muh-Tian Shiue, 2008, 2008 IEEE Custom Integrated Circuits Conference.

High-Accuracy Fixed-Width Booth Multipliers Based on Probability and Simulation

Shyh-Jye Jou, Yuan-Ho Chen, Wen-Quan He, 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

Analog Multilevel Simulation

A. Richard Newton, Shyh-Jye Jou, Resve Saleh, 1994 .

A jointed mode detection and symbol detection scheme for DVB-T

Wei-Chang Liu, Shyh-Jye Jou, Wei-Ting Chen, 2008, IEEE Trans. Consumer Electron..

Sub-word and reduced-width Booth multipliers for DSP applications

Shyh-Jye Jou, Yi-Ting Chen, Meng-Hung Tsai, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques

Shyh-Jye Jou, Yuan-Hua Chu, Chia-Wen Chang, 2016, IEICE Trans. Electron..

A 802.15.3c/802.11ad compliant 24 Gb/s FFT processor for 60 GHz communication systems

Wei-Chang Liu, Shyh-Jye Jou, Henry Lopez Davila, 2015, 2015 28th IEEE International System-on-Chip Conference (SOCC).

Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design

Ming-Hsien Tu, Shyh-Jye Jou, Li-Rong Wang, 2011, IEICE Trans. Electron..

Decentralized BIST Methodology for System Level Interconnects

Shyh-Jye Jou, Chauchin Su, 1999, J. Electron. Test..

Near-threshold all-digital PLL with dynamic voltage scaling power management

Shyh-Jye Jou, Kuo-Chiang Chang, Yuan-Hua Chu, 2016 .

Dual-Mode All-Digital Baseband Receiver With a Feed-Forward and Shared-Memory Architecture for Dual-Standard Over 60 GHz NLOS Channel

Wei-Chang Liu, Shyh-Jye Jou, Chun-Yi Liu, 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression

Shyh-Jye Jou, Wei-Zen Chen, Chao-Cheng Lee, 2015, IEEE Trans. Circuits Syst. I Regul. Pap..

Low-power multiplierless FIR filter synthesizer based on CSD code

Shyh-Jye Jou, Chin-Hung Lin, Maw-Ching Lin, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array

Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, 2012, Proceedings of Technical Program of 2012 VLSI Design, Automation and Test.

Low-error reduced-width Booth multipliers for DSP applications

Shyh-Jye Jou, Meng-Hung Tsai, Ya-Lan Tsao, 2003 .

Concurrent Digital Adaptive Decision Feedback Equalizer for 10GBase-LX4 Ethernet System

Shyh-Jye Jou, Yu-Chun Lin, Chi-Shiung Lin, 2007, 2007 IEEE Custom Integrated Circuits Conference.

A design flow for multiplierless linear-phase FIR filters: from system specification to Verilog code

An-Yeu Wu, Shyh-Jye Jou, Kai-Yuan Jheng, 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

A pitch based VAD adopting quasi-ANSI 1/3 octave filter bank with 11.3 ms latency for monosyllable hearing aids

Shyh-Jye Jou, Yi-Cheng Huang, Fan-Chiang Yi, 2013, SiPS 2013 Proceedings.

An all-digital bit transistor characterization scheme for CMOS 6T SRAM array

Ming-Chien Tsai, Yi-Wei Lin, Wei-Chiang Shih, 2012, 2012 IEEE International Symposium on Circuits and Systems.

A micro-network on chip with 10-Gb/s transmission link

Wei-Chang Liu, Shyh-Jye Jou, Chih-Hsien Lin, 2009, 2009 IEEE Asian Solid-State Circuits Conference.

Low power InfomaxICA with compensation strategy for binaural hearing-aid

Shyh-Jye Jou, Tai-Shih Chi, Ching-Wen Huang, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

An 8X-Parallelism Memory Access Reordering Polyphase Network for 60 GHz FBMC-OQAM Baseband Receiver

Wei-Chang Liu, Shyh-Jye Jou, Henry Lopez Davila, 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

Mixed-mode simulation and analog multilevel simulation

A. Richard Newton, Resve A. Saleh, Shyh-Jye Jou, 1994, The Kluwer international series in engineering and computer science.

Symbol and carrier frequency offset synchronization for IEEE802.16e

Shyh-Jye Jou, Ting-Chen Wei, Hsiao-Yun Chen, 2008, 2008 IEEE International Symposium on Circuits and Systems.

A low-power body-channel communication system for binaural hearing aids

Tzu-Hsien Sang, Shyh-Jye Jou, Tian-Sheuan Chang, 2012, 2012 IEEE Biomedical Circuits and Systems Conference (BioCAS).

A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist

Chien-Yu Lu, Ming-Hsien Tu, Kuen-Di Lee, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Digital Self-Healing using Smart Sensing Technique for IQ Mismatch and LO Leakage against Non-Flat Path Response in mmWave Communication System

Shyh-Jye Jou, Hung-Chih Liu, Chih-Wei Jen, 2020, 2020 IEEE International Symposium on Circuits and Systems (ISCAS).

Low power correlator of DSP core for communication system

Shyh-Jye Jou, Ya-Lan Tsao, Maw-Ching Lin, 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

Adaptive AC/DC output buffer with reduced ground bounce and output ringing

Shyh-Jye Jou, Shu-Hua Kuo, Jui-Ta Chiu, 2000, Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434).

A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications

Shyh-Jye Jou, Hsie-Chia Chang, Chen-Yi Lee, 2012, IEEE Journal of Solid-State Circuits.

Gate-Level Simulation

A. Richard Newton, Shyh-Jye Jou, Resve Saleh, 1985, IEEE Design & Test of Computers.

Parasitic effect removal for analog measurement in P1149.4 environment

Shyh-Jye Jou, Chauchin Su, Yue-Tsang Chen, 1997, Proceedings International Test Conference 1997.

Metrology for analog module testing using analog testability bus

Shyh-Jye Jou, Chauchin Su, Yue-Tsang Chen, 1996, Proceedings of International Conference on Computer Aided Design.

A Digital Golay-MPIC Time Domain Equalizer for SC/OFDM Dual-Modes at 60 GHz Band

Wei-Chang Liu, Shyh-Jye Jou, Ting-Chen Wei, 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control

Hao-I Yang, Ming-Hsien Tu, Nan-Chun Lien, 2013, 2013 IEEE International SOC Conference.

4/2 PAM Pre-emphasis Transmitter with Combined Driver and Mux

Shyh-Jye Jou, Chih-Hsien Lin, 2005, 2005 IEEE Asian Solid-State Circuits Conference.

A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression

Shyh-Jye Jou, Wei-Zen Chen, Chao-Cheng Lee, 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

Design and analysis of digital data recovery circuits using oversampling

Shyh-Jye Jou, Chih-Hsien Lin, Yen-Hung Chen, 2007, IET Circuits Devices Syst..

Memory reduction ICFO estimation architecture for DVB-T

Shyh-Jye Jou, Muh-Tian Shiue, Ting-Zhen Wei, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Adaptive on-die termination resistors for high-speed transceiver

Shyh-Jye Jou, Chih-Ning Chen, Chih Hsien Lin, 2005, 2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test, 2005. (VLSI-TSA-DAT)..

40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist

Ming-Hsien Tu, Shyh-Jye Jou, Ching-Te Chuang, 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

A 40Gb/s All-Digital Adaptive Noise-Suppression Feed-Forward Filter and Adaptive Decision Feedback Equalizer with 40 parallelisms for 2-PAM Systems

Wei-Chang Liu, Shyh-Jye Jou, Yu-Chun Lin, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

A 6Gbps Serial Link Transmitter with Pre-emphasis

Shyh-Jye Jou, Chang-Min Chu, Chih-Hua Chuang, 2007 .

A 0.92mm2 23.4mW fully-compliant CTC decoder for WiMAX 802.16e application

Shyh-Jye Jou, Hsie-Chia Chang, Chen-Yi Lee, 2009, 2009 IEEE Custom Integrated Circuits Conference.

Low-jitter transmission code for 4-PAM signaling in serial links

Shyh-Jye Jou, Chih-Hsien Lin, Hsiao-Yun Chen, 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.

Synthesizable Injection-Locked Phase-Locked Loop with Multiphase Interlocking Digitally Controlled Oscillator Arrays

Shyh-Jye Jou, Yu-Cheng Su, Kang-Yu Chang, 2019, 2019 IEEE 13th International Conference on ASIC (ASICON).

Two-Stage Scattered Pilot Synchronization with Channel Estimation Scattered Pilots Pre-Filling for DVB-T/H

Wei-Chang Liu, Shyh-Jye Jou, Ting-Chen Wei, 2007, 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Current and power waveforms simulator of CMOS circuits

Shyh-Jye Jou, Jhy Haur Pan, Wen Hsing Hsieh, 1997 .

A 0.33-V, 500-kHz, 3.94-$\mu\hbox{W}$ 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist

Chien-Yu Lu, Hao-I Yang, Ming-Hsien Tu, 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

elined Multiplier-Accumulator Usin Low-Power Static and Dynamic Full

Shyh-Jye Jou, Chang-Yu Chen, En-Chung Yang, 1997 .

Hierarchical techniques for symbolic analysis of large electronic circuits

Shyh-Jye Jou, Chauchin Su, Mei-Fang Perng, 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.

DC-Balance Low-Jitter Transmission Code for 4-PAM Signaling

Shyh-Jye Jou, Chih-Hsien Lin, Hsiao-Yun Chen, 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

Parameterized and low power DSP core for embedded systems

Shyh-Jye Jou, Ya-Lan Tsao, Ming Hsuan Tan, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

An event-driven incremental timing fault simulator

Shyh-Jye Jou, Wen Zen Shen, Shwu-Huey Chiou, 1991, 1991 International Symposium on VLSI Technology, Systems, and Applications - Proceedings of Technical Papers.

A 5.7Gbps row-based layered scheduling LDPC decoder for IEEE 802.15.3c applications

Shyh-Jye Jou, Hsie-Chia Chang, Chen-Yi Lee, 2010, 2010 IEEE Asian Solid-State Circuits Conference.

Novel Programmable FIR Filter Based on Higher Radix Recoding for Low-Power and High-Performance Applications

Shyh-Jye Jou, Hsiao-Yun Chen, 2007, 2007 IEEE International Conference on Acoustics, Speech and Signal Processing - ICASSP '07.

High throughput concurrent lookahead adaptive decision feedback equaliser

Shyh-Jye Jou, Muh-Tian Shiue, Yu-Chun Lin, 2012, IET Circuits Devices Syst..

An embedded DSP core for wireless communication

Shyh-Jye Jou, Yi-Ting Chen, Hsiao Ping Lee, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

A subthreshold SRAM with embedded data-aware write-assist and adaptive data-aware keeper

Shyh-Jye Jou, Ching-Te Chuang, Yi-Wei Chiu, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Low complexity synchronization design of an OFDM receiver for DVB-T/H

Wei-Chang Liu, Shyh-Jye Jou, Ting-Chen Wei, 2009, IEEE Transactions on Consumer Electronics.

EVENT-DRIVEN INCREMENTAL TIMING FAULT SIMULATOR

Shyh-Jye Jou, Wen Zen Shen, Y.-S. Tao, 1993 .

十億級資料傳輸室內無線 SC/OFDM 接收器之系統架構設計與相位雜訊消除演算法及設計

Shyh-Jye Jou, 周世傑, Liang-Yu Huang, 2014 .

5 Gbps serial link transmitter with pre-emphasis

Shyh-Jye Jou, Chih-Hsien Lin, Chung-Hong Wang, 2003, Proceedings of the ASP-DAC Asia and South Pacific Design Automation Conference, 2003..

A parallel event-driven MOS timing simulator on distributed-memory multiprocessors

Shyh-Jye Jou, Chauchin Su, Wen-Hsing Hsieh, 1995, Proceedings of ISCAS'95 - International Symposium on Circuits and Systems.

A SC/OFDM dual mode frequency-domain equalizer for 60GHz multi-gbps wireless transmission

Wei-Chang Liu, Shyh-Jye Jou, Ting-Chen Wei, 2011, Proceedings of 2011 International Symposium on VLSI Design, Automation and Test.

A 50 Gb/s Adaptive Dual Data-Paths NS-EICL ADFE with 50 Parallelisms for 2-PAM Systems

Shyh-Jye Jou, Kang-Lun Chiu, Chee-Kit Ng, 2019, 2019 IEEE International Symposium on Circuits and Systems (ISCAS).

A portable inspection system to estimate direct glare of various LED modules

Shyh-Jye Jou, Wei-Jei Peng, Pei-Li Sun, 2015, International Conference on Optical and Photonic Engineering.

A memory access reordering polyphase network for 60 GHz FBMC-OQAM baseband receiver

Shyh-Jye Jou, Chun-Yi Liu, Chih-Wei Jen, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

應用於一百五十億位元室內無線 SC/OFDM接收機之等化器與基頻設計

Shyh-Jye Jou, Chia-Chun Tsui, 周世傑, 2012 .

Decentralized BIST for 1149.1 and 1149.5 based interconnects

Shyh-Jye Jou, Chauchin Su, Yuan-Tzu Ting, 1996, Proceedings ED&TC European Design and Test Conference.

An all digital phase-locked loop with modified binary search of frequency acquisition

Shyh-Jye Jou, Ya-Lan Tsao, I-YingYang, 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

An efficient 18-band quasi-ANSI 1/3-octave filter bank using re-sampling method for digital hearing aids

Shyh-Jye Jou, Cheng-Yen Yang, Chih-Wei Liu, 2014, 2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

Power and area reduction in multi-stage addition using operand segmentation

Wei-Chang Liu, Shyh-Jye Jou, Chia-Hsiang Yang, 2013, 2013 International Symposium onVLSI Design, Automation, and Test (VLSI-DAT).

An IEEE 802.15.3c/802.11ad compliant SC/OFDM dual-mode baseband receiver for 60 GHz Band

Wei-Chang Liu, Shyh-Jye Jou, Ting-Chen Wei, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Design of carrier recovery for QAM/VSB dual mode

Shyh-Jye Jou, Hsin-Yi Lin, Chrong-Kuang Wang, 2002, IEEE 2002 International Conference on Communications, Circuits and Systems and West Sino Expositions.

A module generator for parameterized DSP core

Shyh-Jye Jou, Wei-Hao Chen, Bo-Shiang Huang, 2004, The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings..

Intrinsic response for analog module testing using an analog testability bus

Shyh-Jye Jou, Chauchin Su, Yue-Tsang Chen, 2001, TODE.

Adaptive Quadrature Clock Generator

Shyh-Jye Jou, Chih Hsien Lin, Juin-Hau Huang, 2006, 2006 International Symposium on VLSI Design, Automation and Test.

單一載波、正交分頻多工、濾波器組三模組基頻接收機系統於60GHZ頻帶應用

Shyh-Jye Jou, Meng-Siou Sie, 周世傑, 2015 .

Structural approach for performance driven ECC circuit synthesis

Shyh-Jye Jou, Chauchin Su, E. Y. Chen, 1997, Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference.

A reconfigurable MAC architecture implemented with mixed-Vt standard cell library

Ming-Hsien Tu, Shyh-Jye Jou, Li-Rong Wang, 2008, 2008 IEEE International Symposium on Circuits and Systems.

SIMULATABLE TIMING MODEL FOR MOS LOGIC-CIRCUIT

Chein-Wei Jen, Shyh-Jye Jou, Wen Zen Shen, 1987 .

Interference measurement and analysis of full-duplex wireless system in 60 GHz band

Bingli Jiao, Shyh-Jye Jou, Xuefeng Yin, 2016, 2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS).

A 802.15.3c/802.11ad dual mode phase noise cancellation for 60 GHz communication systems

Wei-Chang Liu, Shyh-Jye Jou, Chun-Yi Liu, 2015, VLSI Design, Automation and Test(VLSI-DAT).

Low-power multirate IF digital frequency down converter

Shyh-Jye Jou, Chorng-Kuang Wang, Shou-Yang Wu, 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).

Introduction to the Special Section on the 2007 Asian Solid-State Circuits Conference (A-SSCC'07)

Shyh-Jye Jou, Nicky Lu, 2008, IEEE J. Solid State Circuits.

Parallelism of circuit simulation on array processor

Shyh-Jye Jou, C.-W. Jen, W.-Z. Shen, 1991, 1991., IEEE International Sympoisum on Circuits and Systems.

Multiplierless multirate decimator/interpolator module generator

Shyh-Jye Jou, Kai-Yuan Jheng, An-Yeu Wu, 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.

Low-power globally asynchronous locally synchronous design using self-timed circuit technology

Shyh-Jye Jou, I-Yao Chuang, 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.

Low-power digital CDMA receiver

Shyh-Jye Jou, Yi-Chen Tsai, Ja-Sheng Liu, 2003, ASP-DAC '03.

60GHz室內無線Gb/s SC/OFDM基頻接收器的FPGA 雛型設計

Pranav Arya, Shyh-Jye Jou, 周世傑, 2015 .

A Robust Channel Estimator for High-Mobility STBC-OFDM Systems

Shyh-Jye Jou, Chia-Chi Huang, Meng-Lin Ku, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

Blind ICA detection based on second-order cone programming for MC-CDMA systems

Shyh-Jye Jou, Chih-Wei Jen, 2014, EURASIP J. Adv. Signal Process..

Analysis and implementation of low-power perceptual multiband noise reduction for the hearing aids application

Shyh-Jye Jou, Tian-Sheuan Chang, Cheng-Wen Wei, 2014, IET Circuits Devices Syst..

MOTA - AN MOS TIMING SIMULATOR.

Shyh-Jye Jou, Chung Len Lee, Wen Zen Shen, 1984 .

MOTA: a MOSFET timing simulator

Shyh-Jye Jou, Wen-Zen Shen, Chih-Wei Jen, 1986 .

A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control

Yi-Wei Lin, Hao-I Yang, Wei-Chiang Shih, 2011, 2011 IEEE International SOC Conference.

Low Power and Power Aware Design for DVB-T/H Baseband Inner Receiver

Wei-Chang Liu, Shyh-Jye Jou, Ting-Chen Wei, 2007, 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

Low-power multirate architecture for IF digital frequency down converter

Shyh-Jye Jou, Chorng-Kuang Wang, Shou-Yang Wu, 1998 .

Parallel event-driven MOS timing simulator on distributed memory multiprocessors

Shyh-Jye Jou, Chauchin Su, W.-H. Hsieh, 1996 .

VLSI implementation of timing recovery and carrier recovery for QAM/VSB dual mode

Shyh-Jye Jou, Chrong-Kuang Wang, Muh-Tian Shiau, 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).

Impulse response fault model and fault extraction for functional level analog circuit diagnosis

Shyh-Jye Jou, Chauchin Su, Shenshung Chiang, 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

A SC/HSI dual-mode baseband receiver with frequency-domain equalizer for IEEE 802.15.3c

Wei-Chang Liu, Shyh-Jye Jou, Ting-Chen Wei, 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).

Benchmark circuits for mixed-mode simulators

Shyh-Jye Jou, Resve Saleh, D. Overhauser, 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

A 3.52 Gb/s mmWave baseband with delayed decision feedback sequence estimation in 40 nm

Wei-Chang Liu, Shyh-Jye Jou, Andreas Peter Burg, 2015, 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A Near-Threshold Cell-Based All-Digital PLL with Hierarchical Band-Selection G-DCO for Fast Lock-In and Low-Power Applications

Shyh-Jye Jou, Yuan-Hua Chu, Chia-Wen Chang, 2015, IEICE Trans. Electron..

Hardware nested loop with buffer of parameterized and embedded DSP core

Shyh-Jye Jou, Ya Lan Tsao, Wei Hao Chen, 2005 .

A new VSB modulation technique and shaping filter design

Shyh-Jye Jou, Muh-Tian Shiue, Chorng-Kuang Wang, 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

Syndrome simulation and syndrome test for unscanned interconnects

Shyh-Jye Jou, Chauchin Su, Yuan-Tzu Ting, 1996, Proceedings of the Fifth Asian Test Symposium (ATS'96).

Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist

Ming-Chien Tsai, Ming-Hsien Tu, Shyh-Jye Jou, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Digital Two-Stage Phase Noise Compensation and rCFO/rSCO Tracking Module for mmW Single Carrier Systems

Shyh-Jye Jou, Kang-Lun Chiu, Hsun-Wei Chan, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Robust Model Mapping Optimization For Non-Ideal Computing In-Memory

Shyh-Jye Jou, Tuo-Hung Hou, Tian-Sheuan Chang, 2021 .

A Reconfigurable In-SRAM Computing Architecture for DCNN Applications

Shyh-Jye Jou, Chia-Lin Hu, Kang-Yu Chang, 2021, 2021 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

A Low-Jitter ADPLL with Adaptive High-Order Loop Filter and Fine Grain Varactor Based DCO

Shyh-Jye Jou, Hossameldin A. Ibrahim, Kang-Yu Chang, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).

A 5 . 7 Gbps Row-Based Layered Scheduling LDPC Decoder for IEEE 802 . 15 . 3 c Applications

Shyh-Jye Jou, Hsie-Chia Chang, Chih-Lung Chen, .

Delay-difference DLL and its-application on skewed output buffer

Shyh-Jye Jou, Ya-Lan Tsao, Ming-Chao Chung, 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.