K. Ishii

Low-jitter, low-power 2.5-Gb/s one-chip optical receiver IC with 1:8 DEMUX

Keiji Kishine, Haruhiko Ichino, Masaki Hirose, 1999, Proceedings of the 1999 Bipolar/BiCMOS Circuits and Technology Meeting (Cat. No.99CH37024).

Master-Slave Toggle Flip-Flop Circuit

Haruhiko Ichino, K. Ishii, Chikara Yamaguchi, 1994 .

50 Gbit/s low-jitter dynamic decision circuit using Cbc compensation and semi-feed forward techniques

Hideyuki Nosaka, K. Ishii, Takatomo Enoki, 2003 .

Recent progress in 40- To 100-Gbit/s-class optical communications ICS using InP-based HBT technologies

Hideyuki Nosaka, Kimikazu Sano, K. Ishii, 2005 .

3.21 ps ECL gate using InP/InGaAs DHBT technology

Hideyuki Nosaka, K. Ishii, Kenji Kurishima, 2003 .

Maximum operating frequency in Si bipolar master-slave toggle flip-flop circuit

Haruhiko Ichino, K. Ishii, C. Yamaguchi, 1994 .

A Jitter Suppression Technique for a Clock Multiplier

Keiji Kishine, Haruhiko Ichino, K. Ishii, 2000 .

90 Gbit/s 0.5 W decision circuit using InP/InGaAs double heterojunction bipolar transistors

Kimikazu Sano, Koichi Murata, K. Ishii, 1996 .

A 10-Gb/s data-pattern independent clock and data recovery circuit with a two-mode phase comparator

Hideyuki Nosaka, K. Ishii, Takatomo Enoki, 2003 .