Yong Lim

26.1 A 1mW 71.5dB SNDR 50MS/S 13b fully differential ring-amplifier-based SAR-assisted pipeline ADC

Michael P. Flynn, Yong Lim, M. Flynn, 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

A 100 MS/s, 10.5 Bit, 2.46 mW Comparator-Less Pipeline ADC Using Self-Biased Ring Amplifiers

Michael P. Flynn, Yong Lim, 2015, IEEE Journal of Solid-State Circuits.

11.5 A 100MS/s 10.5b 2.46mW comparator-less pipeline ADC using self-biased ring amplifiers

Michael P. Flynn, Yong Lim, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

A non-exact-multiplication scheme for digital filter implementation using bit-slice components

Yong Lim, 1985 .

An interpolation technique for computing the DFT of a sparse sequence

Yong Lim, 1985, IEEE Trans. Acoust. Speech Signal Process..

A calibration-free 2.3 mW 73.2 dB SNDR 15b 100 MS/s four-stage fully differential ring amplifier based SAR-assisted pipeline ADC

Michael P. Flynn, Yong Lim, 2017, 2017 Symposium on VLSI Circuits.

A fully integrated reprogrammable memristor–CMOS system for efficient multiply–accumulate operations

Zhengya Zhang, Yong Lim, Wei Lu, 2019, Nature Electronics.

A 1.5-GHz 6.144T Correlations/s 64 $\times $ 64 Cross-Correlator With 128 Integrated ADCs for Real-Time Synthetic Aperture Imaging

Michael P. Flynn, Chia-Hsiang Chen, Zhengya Zhang, 2017, IEEE Journal of Solid-State Circuits.

A 1 mW 71.5 dB SNDR 50 MS/s 13 bit Fully Differential Ring Amplifier Based SAR-Assisted Pipeline ADC

Michael P. Flynn, Yong Lim, M. Flynn, 2015, IEEE Journal of Solid-State Circuits.

A 16-channel noise-shaping machine learning analog-digital interface

Michael P. Flynn, Yong Lim, Adam E. Mendrela, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

A 1.1e- temporal noise 1/3.2-inch 8Mpixel CMOS image sensor using pseudo-multiple sampling

Kyungmin Kim, Hansoo Lee, Han Yang, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).