B. Previtali

发表

25nm Short and Narrow Strained FDSOI with TiN/HfO2 Gate Stack

O. Faynot, F. Andrieu, T. Ernst, 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..

Sub-100nm high-K metal gate GeOI pMOSFETs performance: Impact of the Ge channel orientation and of the source injection velocity

M. Vinet, J.-M. Hartmann, E. Augendre, 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

Fully Depleted SOI MOSFETs with WSix metal gate on HfO2 gate dielectric

M. Vinet, D. Lafond, S. Deleonibus, 2006, 2006 IEEE international SOI Conferencee Proceedings.

Experimental gate misalignment analysis on double gate SOI MOSFETs

M. Vinet, S. Deleonibus, J. Widiez, 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

Analytical modeling of Accumulation-Mode Suspended-Gate MOSFET and process challenges for very low operating power devices

G. Ghibaudo, M. Vinet, T. Ernst, 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

Multiple gate devices: advantages and challenges

O. Faynot, M. Vinet, S. Deleonibus, 2005 .

TiN metal gate thickness influence on fully depleted SOI MOSFETs physical and electrical properties

M. Vinet, S. Deleonibus, J. Widiez, 2005, 2005 IEEE International SOI Conference Proceedings.

Multigate silicon MOSFETs for 45 nm node and beyond

O. Faynot, Maud Vinet, S. Deleonibus, 2006 .

First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers

O. Faynot, P. Batude, M. Vinet, 2016, 2016 IEEE Symposium on VLSI Technology.

A new Si:C epitaxial channel nMOSFET architecture with improved drivability and short-channel characteristics

T. Ernst, J.-M. Hartmann, S. Deleonibus, 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

Experimental characterization of source-to-drain tunneling in 10nm SOI devices

M. Vinet, S. Deleonibus, B. Previtali, 2005, 2005 IEEE International SOI Conference Proceedings.

New and accurate method for electrical extraction of silicon film thickness on fully-depleted SOI and double gate transistors

M. Vinet, S. Deleonibus, J. Widiez, 2004, 2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573).

Recent advances in low temperature process in view of 3D VLSI integration

X. Garros, G. Cibrario, P. Batude, 2016, 2016 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Will strain be useful for 10nm quasi-ballistic FDSOI devices? An experimental study

O. Faynot, M. Vinet, F. Andrieu, 2007, 2007 IEEE Symposium on VLSI Technology.

Monolithic 3D integration: A powerful alternative to classical 2D scaling

O. Rozeau, O. Faynot, G. Cibrario, 2014, 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Fabrication of a novel strained SiGe:C-channel planar 55 nm nMOSFET for high-performance CMOS

G. Guegan, T. Ernst, J.-M. Hartmann, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

Strained tunnel FETs with record ION: first demonstration of ETSOI TFETs with SiGe channel and RSD

O. Faynot, F. Andrieu, O. Weber, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Experimental comparison between double gate, ground plane, and single gate SOI CMOSFETs

S. Deleonibus, J. Widiez, B. Previtali, 2004, Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850).

Recent advances in 3D VLSI integration

G. Cibrario, P. Batude, M. Vinet, 2016, 2016 International Conference on IC Design and Technology (ICICDT).

Low temperature FDSOI devices, a key enabling technology for 3D sequential integration

P. Batude, M. Vinet, B. Previtali, 2013, 2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Advances, challenges and opportunities in 3D CMOS sequential integration

J. Mazurier, O. Faynot, P. Batude, 2011, 2011 International Electron Devices Meeting.

Single dopant impact on electrical characteristics of SOI NMOSFETs with effective length down to 10nm

O. Faynot, M. Vinet, B. Previtali, 2010, 2010 Symposium on VLSI Technology.

Insights in accesses optimization for nFET low temperature Fully Depleted Silicon On Insulator devices

G. Ghibaudo, P. Batude, M. Vinet, 2014, 2014 International Workshop on Junction Technology (IWJT).

Demonstration of low temperature 3D sequential FDSOI integration down to 50 nm gate length

O. Faynot, P. Batude, M. Vinet, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

FDSOI nanowires: An opportunity for hybrid circuit with field effect and single electron transistors

O. Faynot, M. Vinet, L. Grenouillet, 2013, 2013 IEEE International Electron Devices Meeting.

FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration

Maud Vinet, Claire Fenouillet-Beranger, D. Lafond, 2015 .

Improvements in low temperature (<625°C) FDSOI devices down to 30nm gate length

X. Garros, J. Mazurier, O. Faynot, 2012, Proceedings of Technical Program of 2012 VLSI Technology, System and Application.

7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing

F. Andrieu, B. Previtali, S. Barraud, 2020, 2020 IEEE Symposium on VLSI Technology.

Self-Aligned Planar Double-Gate MOSFETs by Bonding for 22-nm Node, With Metal Gates, High- $\kappa$ Dielectrics, and Metallic Source/Drain

M. Vinet, D. Lafond, S. Deleonibus, 2009, IEEE Electron Device Letters.

Performance and design considerations for gate-all-around stacked-NanoWires FETs

O. Rozeau, M. Vinet, F. Andrieu, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Experimental evaluation of gate architecture influence on DG SOI MOSFETs performance

M. Vinet, S. Deleonibus, J. Widiez, 2005, IEEE Transactions on Electron Devices.

3D Sequential Integration: Application-driven technological achievements and guidelines

X. Garros, O. Rozeau, O. Faynot, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

First integration of Ni0.9Co0.1 on pMOS transistors

P. Batude, M. Vinet, M. Haond, 2016, 2016 IEEE International Interconnect Technology Conference / Advanced Metallization Conference (IITC/AMC).

A new step in GeOI pFET scaling and Off-State current reduction: 30nm gate length and record ION/IOFF ratio

O. Faynot, M. Vinet, D. Lafond, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

Tunability of Parasitic Channel in Gate-All-Around Stacked Nanosheets

O. Rozeau, M. Vinet, J. Lacord, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

FDSOI devices: A solution to achieve low junction leakage with low temperature processes (≤ 650°C)

O. Faynot, P. Batude, S. Cristoloveanu, 2012, 2012 13th International Conference on Ultimate Integration on Silicon (ULIS).

nFET FDSOI activated by low temperature solid phase epitaxial regrowth: Optimization guidelines

G. Ghibaudo, P. Batude, M. Vinet, 2014, 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

Bonded planar double-metal-gate NMOS transistors down to 10 nm

M. Vinet, D. Lafond, S. Deleonibus, 2005, IEEE Electron Device Letters.

GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current

O. Faynot, M. Vinet, C. Tabone, 2010, IEEE Electron Device Letters.

GeOI and SOI 3D monolithic cell integrations for high density applications

X. Garros, O. Rozeau, O. Faynot, 2006, 2009 Symposium on VLSI Technology.

New insights on bottom layer thermal stability and laser annealing promises for high performance 3D VLSI

X. Garros, P. Batude, M. Vinet, 2014, 2014 IEEE International Electron Devices Meeting.

Dual metallic source and drain integration on planar Single and Double Gate SOI CMOS down to 20nm: Performance and scalability assessment

O. Faynot, M. Vinet, D. Lafond, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).