Aibin Yan

发表

LCHR-TSV: Novel Low Cost and Highly Repairable Honeycomb-Based TSV Redundancy Architecture for Clustered Faults

Lin Lu, Huaguo Liang, Tianming Ni, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Novel Quadruple Cross-Coupled Memory Cell Designs With Protection Against Single Event Upsets and Double-Node Upsets

Patrick Girard, Zhengfeng Huang, Jun Zhou, 2019, IEEE Access.

Highly Robust Double Node Upset Resilient Hardened Latch Design

Xin Li, Huaguo Liang, Zhengfeng Huang, 2017, IEICE Trans. Electron..

Information Assurance Through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation Environment

Zhili Chen, Tianming Ni, Zhengfeng Huang, 2020, IEEE Transactions on Computers.

Aging-Temperature-and-Propagation Induced Pulse-Broadening Aware Soft Error Rate Estimation for nano-Scale CMOS

Kang Yang, Maoxiang Yi, Aibin Yan, 2018, 2018 IEEE 27th Asian Test Symposium (ATS).

Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation Environments

Zhili Chen, Zhengfeng Huang, Tianming Ni, 2022, IEEE Transactions on Emerging Topics in Computing.

Novel Double-Node-Upset-Tolerant Memory Cell Designs Through Radiation-Hardening-by-Design and Layout

Jie Song, Zhen Wu, Xiaoqing Wen, 2019, IEEE Transactions on Reliability.

A Novel TDMA-Based Fault Tolerance Technique for the TSVs in 3D-ICs Using Honeycomb Topology

Yang Zhao, Xiaoqing Wen, Zhengfeng Huang, 2021, IEEE Transactions on Emerging Topics in Computing.

A Novel Triple-Node-Upset-Tolerant CMOS Latch Design using Single-Node-Upset-Resilient Cells

Huaguo Liang, Xuejun Li, Zhengfeng Huang, 2019, 2019 IEEE International Test Conference in Asia (ITC-Asia).

Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory

Ying Sun, Huaguo Liang, Zhengfeng Huang, 2019, 2019 IEEE 37th VLSI Test Symposium (VTS).

Design of a Novel Self-Recoverable SRAM Cell Protected Against Soft Errors

Zhen Wu, Tianming Ni, Jun Zhou, 2020, 2019 6th International Conference on Dependable Systems and Their Applications (DSA).

Pattern Reorder for Test Cost Reduction Through Improved SVMRANK Algorithm

Huaguo Liang, Tianming Ni, Zhengfeng Huang, 2020, IEEE Access.

A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace Applications

Patrick Girard, Zhengfeng Huang, Aibin Yan, 2020, IEEE Transactions on Aerospace and Electronic Systems.

A single event transient detector in SRAM-based FPGAs

Huaguo Liang, Zhengfeng Huang, Xiumin Xu, 2017, IEICE Electron. Express.

Novel Radiation Hardened Latch Design with Cost-Effectiveness for Safety-Critical Terrestrial Applications

Patrick Girard, Zhili Chen, Zhen Wu, 2019, 2019 IEEE 28th Asian Test Symposium (ATS).

A transient pulse dually filterable and online self-recoverable latch

Huaguo Liang, Zhengfeng Huang, Aibin Yan, 2017, IEICE Electron. Express.

An SEU resilient, SET filterable and cost effective latch in presence of PVT variations

Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, 2016, Microelectron. Reliab..

Design of a Sextuple Cross-Coupled SRAM Cell with Optimized Access Operations for Highly Reliable Terrestrial Applications

Patrick Girard, Jun Zhou, Zhen Wu, 2019, 2019 IEEE 28th Asian Test Symposium (ATS).

T2FA: Transparent Two-Factor Authentication

Zheng Qin, Jiliang Zhang, Aibin Yan, 2018, IEEE Access.

HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical Applications

Patrick Girard, Xiaoqing Wen, Aibin Yan, 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications

Xiaoqing Wen, Jie Song, Aibin Yan, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical Applications

Huaguo Liang, Zhengfeng Huang, Xiaoqing Wen, 2020, ISCAS.

A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application

Xiaoqing Wen, Zhengfeng Huang, Kang Yang, 2019, IEEE Transactions on Circuits and Systems II: Express Briefs.

A Cost-Effective TSV Repair Architecture for Clustered Faults in 3-D IC

Huaguo Liang, Tianming Ni, Zhengfeng Huang, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Design of a Radiation Hardened Latch for Low-Power Circuits

Huaguo Liang, Zhengfeng Huang, Zhi Wang, 2014, 2014 IEEE 23rd Asian Test Symposium.

A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node Upsets

Tianming Ni, Jun Zhou, Patrick Girard, 2020, 2020 IEEE 29th Asian Test Symposium (ATS).

A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology

Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, 2015, IEICE Trans. Electron..

Architecture of Cobweb-Based Redundant TSV for Clustered Faults

Huaguo Liang, Qi Xu, Tianming Ni, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Radiation Hardening by Design of a Novel Double-Node-Upset-Tolerant Latch Combined with Layout Technique

Zhengfeng Huang, Jing Guo, Xiangsheng Fang, 2018, 2018 IEEE International Test Conference in Asia (ITC-Asia).

Novel Low Cost, Double-and-Triple-Node-Upset-Tolerant Latch Designs for Nano-scale CMOS

Xiaoqing Wen, Zhengfeng Huang, Jing Guo, 2018, IEEE Transactions on Emerging Topics in Computing.

A Region-Based Through-Silicon via Repair Method for Clustered Faults

Huaguo Liang, Zhengfeng Huang, Xiumin Xu, 2017, IEICE Trans. Electron..

Design of a Triple-Node-Upset Self-Recoverable Latch for Aerospace Applications in Harsh Radiation Environments

Kohei Miyase, Xiaoqing Wen, Aibin Yan, 2020, IEEE Transactions on Aerospace and Electronic Systems.

A Methodology for Characterization of SET Propagation in SRAM-Based FPGAs

Huaguo Liang, Zhengfeng Huang, Yiming Ouyang, 2016, IEEE Transactions on Nuclear Science.

Novel low cost and DNU online self-recoverable RHBD latch design for nanoscale CMOS

Zhen Wu, Qian He, Huaguo Liang, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology

Huaguo Liang, Zhengfeng Huang, Yiming Ouyang, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

STAHL: A Novel Scan-Test-Aware Hardened Latch Design

Xiaoqing Wen, Stefan Holst, Aibin Yan, 2019, 2019 IEEE European Test Symposium (ETS).

Intra Coding with Geometric Information for Urban Building Scenes

Aibin Yan, Hua Bao, Qijun Wang, 2020 .

Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch Designs

Jie Song, Patrick Girard, Zhengfeng Huang, 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

High-performance, low-cost, and highly reliable radiation hardened latch design

Huaguo Liang, Cuiyun Jiang, Aibin Yan, 2016 .

Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single- and Double-Node Upsets

Yan Chen, Tianming Ni, Patrick Girard, 2020, IEEE Transactions on Circuits and Systems I: Regular Papers.

Dynamic Prediction of the Heat Demand for Buildings in District Heating Systems

Qie Sun, Zhanyu Ma, Chao Wang, 2013 .

Non-Intrusive Online Distributed Pulse Shrinking-Based Interconnect Testing in 2.5D IC

Huaguo Liang, Zhengfeng Huang, Tianming Ni, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

Hydraulic performance of a new district heating systems with distributed variable speed pumps

Jun Zhao, Hailong Li, Yulong Zhao, 2013 .

Novel Low Cost and Double Node Upset Tolerant Latch Design for Nanoscale CMOS Technology

Huaguo Liang, Zhengfeng Huang, Xiaolin Xu, 2016, 2016 IEEE 25th Asian Test Symposium (ATS).

Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS

Zhengfeng Huang, Yiming Ouyang, Honghui Deng, 2017, Microelectron. J..

HLDTL: High-performance, low-cost, and double node upset tolerant latch design

Huaguo Liang, Zhengfeng Huang, Jie Cui, 2017, 2017 IEEE 35th VLSI Test Symposium (VTS).

Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applications

Xiaoqing Wen, Patrick Girard, Zhengfeng Huang, 2021, Microelectron. J..

Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace Applications

Patrick Girard, Tianming Ni, Aibin Yan, 2021, J. Electron. Test..

A Reliable and Low-Cost Flip-Flop Hardened against Double-Node-Upsets

Aibin Yan, Zhihui He, Liang Ding, 2021, 2021 8th International Conference on Dependable Systems and Their Applications (DSA).

A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation Environments

Xiaoqing Wen, Patrick Girard, Tianming Ni, 2021, ACM Great Lakes Symposium on VLSI.

A Sextuple Cross-Coupled Dual-Interlocked-Storage-Cell based Multiple-Node-Upset Self-Recoverable Latch

Zhengfeng Huang, Tianming Ni, Aibin Yan, 2021, 2021 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH).

TPDICE and Sim Based 4-Node-Upset Completely Hardened Latch Design for Highly Robust Computing in Harsh Radiation

Xiaoqing Wen, Zhengfeng Huang, Aibin Yan, 2021, 2021 IEEE International Symposium on Circuits and Systems (ISCAS).