Jeyavijayan Rajendran

发表

Engineering crossbar based emerging memory technologies

Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

Post-SAT 3: Stripped-Functionality Logic Locking

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2020 .

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking pdf

Hai Zhou, Franco Stellari, Ujjwal Guin, 2020, ArXiv.

Security of Cloud FPGAs: A Survey pdf

Jeyavijayan Rajendran, Ramesh Karri, Chenglu Jin, 2020, ArXiv.

Hardware security: Threat models and metrics

Jeyavijayan Rajendran, Ramesh Karri, Farinaz Koushanfar, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Layout recognition attacks on split manufacturing

Jeyavijayan Rajendran, Jiang Hu, Wenbin Xu, 2019, ASP-DAC.

Trustworthy Hardware Design: Combinational Logic Locking Techniques

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2020 .

The SAT Attack

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2020 .

Design and analysis of ring oscillator based Design-for-Trust technique

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2011, 29th VLSI Test Symposium.

Breaking Analog Locking Techniques

Jeyavijayan Rajendran, Jiang Hu, Edgar Sánchez-Sinencio, 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

What to Lock?: Functional and Parametric Locking

Jeyavijayan Rajendran, Ozgur Sinanoglu, Yiorgos Makris, 2017, ACM Great Lakes Symposium on VLSI.

Post-SAT 1: Point Function-Based Logic Locking

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2020 .

Memristor based programmable threshold logic array

Jeyavijayan Rajendran, Ramesh Karri, Garrett S. Rose, 2010, 2010 IEEE/ACM International Symposium on Nanoscale Architectures.

Special session: Recent developments in hardware security

Jeyavijayan Rajendran, Siddharth Garg, Naghmeh Karimi, 2018, 2018 IEEE 36th VLSI Test Symposium (VTS).

Removal Attacks on Logic Locking and Camouflaging Techniques

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2020, IEEE Transactions on Emerging Topics in Computing.

Detecting malicious modifications of data in third-party intellectual property cores

Jeyavijayan Rajendran, Ramesh Karri, Vivekananda Vedula, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Towards Secure Analog Designs: A Secure Sense Amplifier Using Memristors

Jeyavijayan Rajendran, Ramesh Karri, David H. K. Hoe, 2014, 2014 IEEE Computer Society Annual Symposium on VLSI.

Security analysis of Anti-SAT

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

Keynote: A Disquisition on Logic Locking

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Breaking Analog Locking Techniques via Satisfiability Modulo Theories

Jeyavijayan Rajendran, Jiang Hu, Amr Abuellil, 2019, 2019 IEEE International Test Conference (ITC).

Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction

Jeyavijayan Rajendran, Edgar Sánchez-Sinencio, Jiang Hu, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Thwarting Replication Attack Against Memristor-Based Neuromorphic Computing System

Jeyavijayan Rajendran, Mark Barnell, Wujie Wen, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Design Considerations for Multilevel CMOS/Nano Memristive Memory

Jeyavijayan Rajendran, Garrett S. Rose, Harika Manem, 2012, JETC.

Post-SAT 2: Insertion of SAT-Unresolvable Structures

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2020 .

Regaining Trust in VLSI Design: Design-for-Trust Techniques

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2014, Proceedings of the IEEE.

Testing the Trustworthiness of IC Testing: An Oracle-Less Attack on IC Camouflaging

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2017, IEEE Transactions on Information Forensics and Security.

The cat and mouse in split manufacturing

Jeyavijayan Rajendran, Jiang Hu, Yujie Wang, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Nano-PPUF: A Memristor-Based Security Primitive

Miodrag Potkonjak, Jeyavijayan Rajendran, Ramesh Karri, 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

Nanoelectronic Solutions for Hardware Security

Miodrag Potkonjak, Jeyavijayan Rajendran, Ramesh Karri, 2012, IACR Cryptology ePrint Archive.

TTLock: Tenacious and Traceless Logic Locking: IEEE Hardware Oriented Security and Trust Conference (HOST)

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2007 .

Sneak-path Testing of Memristor-based Memories

Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, 2013, 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems.

Hardware-based attacks to compromise the cryptographic security of an election system

Jeyavijayan Rajendran, Yiorgos Makris, Liwei Zhou, 2016, 2016 IEEE 34th International Conference on Computer Design (ICCD).

A red team/blue team assessment of functional analysis methods for malicious circuit identification

Jeyavijayan Rajendran, Simha Sethumadhavan, Adam Waksman, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

A Disquisition on Logic Locking

Jeyavijayan Rajendran, Ozgur Sinanoglu, Michael Zuzak, 2019 .

The Need for Logic Locking

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2019, Analog Circuits and Signal Processing.

Leveraging Memristive Systems in the Construction of Digital Logic Circuits

Jeyavijayan Rajendran, Ramesh Karri, Garrett S. Rose, 2012, Proceedings of the IEEE.

VLSI testing based security metric for IC camouflaging

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2013, 2013 IEEE International Test Conference (ITC).

Reconciling the IC test and security dichotomy

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2013, 2013 18th IEEE European Test Symposium (ETS).

Hardware Security and Trust: Logic Locking as a Design-for-Trust Solution

Jeyavijayan Rajendran, Ozgur Sinanoglu, Bodhisatwa Mazumdar, 2018, The IoT Physical Layer.

An Energy-Efficient Memristive Threshold Logic Circuit

Jeyavijayan Rajendran, Ramesh Karri, Garrett S. Rose, 2012, IEEE Transactions on Computers.

DFS covert channels on multi-core platforms

Milos Doroslovacki, Jeyavijayan Rajendran, Guru Venkataramani, 2017, 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

CamoPerturb: Secure IC camouflaging for minterm protection

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

When a Patch is Not Enough - HardFails: Software-Exploitable Hardware Bugs pdf

Ahmad-Reza Sadeghi, Jeyavijayan Rajendran, Hareesh Khattri, 2018, ArXiv.

A study on the effectiveness of Trojan detection techniques using a red team blue team approach

Mark Mohammad Tehranipoor, Jeyavijayan Rajendran, Ramesh Karri, 2013, 2013 IEEE 31st VLSI Test Symposium (VTS).

Sneak-Path Testing of Crossbar-Based Nonvolatile Random Access Memories

Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, 2013, IEEE Transactions on Nanotechnology.

Nano Meets Security: Exploring Nanoelectronic Devices for Security Applications

Miodrag Potkonjak, Jeyavijayan Rajendran, Ramesh Karri, 2015, Proceedings of the IEEE.

Blue team red team approach to hardware trust assessment

Jeyavijayan Rajendran, Ramesh Karri, Vinayaka Jyothi, 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).

Globalization of the semiconductor industry and associated supply chains have made integrated circuits increasingly vulnerable to Trojans. Researchers must expand efforts to verify trust in intellectual property cores and ICs.

Jeyavijayan Rajendran, Ramesh Karri, Kurt Rosenfeld, 2011 .

Security of neuromorphic computing: Thwarting learning attacks using memristor's obsolescence effect

Yiran Chen, Jeyavijayan Rajendran, Qing Wu, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Multi-Objective Strategies for Stripped-Functionality Logic Locking

Jeyavijayan Rajendran, Zhaokun Han, Muhammad Yasin, 2020, International Symposium on Circuits and Systems.

Shielding and securing integrated circuits with sensors

Jeyavijayan Rajendran, Ramesh Karri, Farinaz Koushanfar, 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Controlling your control flow graph

Jeyavijayan Rajendran, Ramesh Karri, Arun K. Kanuparthi, 2016, 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

Manufacturing and Security Challenges in 3D Printing

Nektarios Georgios Tsoutsos, Michail Maniatakos, Jeyavijayan Rajendran, 2016 .

Red Teaming a Multi-Colored Bluetooth Bulb

Jeyavijayan Rajendran, Ryan Vrecenar, Stavros Kalafatis, 2019, 2019 IEEE 37th International Conference on Computer Design (ICCD).

Logic encryption: A fault analysis perspective

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Securing pressure measurements using SensorPUFs

Jeyavijayan Rajendran, Ramesh Karri, Jack Tang, 2016, 2016 IEEE International Symposium on Circuits and Systems (ISCAS).

Parallel memristors: Improving variation tolerance in memristive digital circuits

Jeyavijayan Rajendran, Ramesh Karri, Garrett S. Rose, 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

Supply-Chain Security of Digital Microfluidic Biochips

Mohamed Ibrahim, Jeyavijayan Rajendran, Ozgur Sinanoglu, 2016, Computer.

Security analysis of integrated circuit camouflaging

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2013, CCS.

Special Session: Countering IP Security threats in Supply chain

Jeyavijayan Rajendran, Swarup Bhunia, Tamzidul Hoque, 2019, 2019 IEEE 37th VLSI Test Symposium (VTS).

Fault Analysis-Based Logic Encryption

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2015, IEEE Transactions on Computers.

HardFails: Insights into Software-Exploitable Hardware Bugs

Jeyavijayan Rajendran, Hareesh Khattri, Ghada Dessouky, 2019, USENIX Security Symposium.

Fault Analysis-based Logic Encryption (Preprint)

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2013 .

Activation of logic encrypted chips: Pre-test or post-test?

Jeyavijayan Rajendran, Ozgur Sinanoglu, Samah Mohamed Saeed, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

The Cat and Mouse in Split Manufacturing

Jeyavijayan Rajendran, Jiang Hu, Guofeng Li, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Provably-Secure Logic Locking: From Theory To Practice

Jeyavijayan Rajendran, Ozgur Sinanoglu, Abhrajit Sengupta, 2017, CCS.

Belling the CAD: Toward Security-Centric Electronic System Design

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Towards a comprehensive and systematic classification of hardware Trojans

Jeyavijayan Rajendran, Ramesh Karri, Jorge Jimenez, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Is split manufacturing secure?

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Sneak path enabled authentication for memristive crossbar memories

Jeyavijayan Rajendran, Garrett S. Rose, Mesbah Uddin, 2016, 2016 IEEE Asian Hardware-Oriented Security and Trust (AsianHOST).

Trustworthy Hardware: Trojan Detection and Design-for-Trust Challenges

Mark Mohammad Tehranipoor, Jeyavijayan Rajendran, Ramesh Karri, 2011, Computer.

A Brief History of Logic Locking

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2020 .

Shielding heterogeneous MPSoCs from untrustworthy 3PIPs through security-driven task scheduling

Jeyavijayan Rajendran, Ramesh Karri, Chen Liu, 2013, 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

Improving Tolerance to Variations in Memristor-Based Applications Using Parallel Memristors

Jeyavijayan Rajendran, Ramesh Karri, Garrett S. Rose, 2015, IEEE Transactions on Computers.

An Approach to Tolerate Process Related Variations in Memristor-Based Applications

Jeyavijayan Rajendran, Ramesh Karri, Garrett S. Rose, 2011, 2011 24th Internatioal Conference on VLSI Design.

Boolean Circuit Camouflage: Cryptographic Models, Limitations, Provable Results and a Random Oracle Realization

Nasir D. Memon, Giovanni Di Crescenzo, Jeyavijayan Rajendran, 2017, ASHES@CCS.

Physical Unclonable Functions and Intellectual Property Protection Techniques

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2017 .

Trustworthy Hardware: Identifying and Classifying Hardware Trojans

Mark Mohammad Tehranipoor, Jeyavijayan Rajendran, Ramesh Karri, 2010, Computer.

Securing Processors Against Insider Attacks: A Circuit-Microarchitecture Co-Design Approach

Jeyavijayan Rajendran, Ramesh Karri, Mohamed Zahran, 2013, IEEE Design & Test.

High-level synthesis for security and trust

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2013, 2013 IEEE 19th International On-Line Testing Symposium (IOLTS).

Pre-SAT Logic Locking

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2020 .

Hardware security strategies exploiting nanoelectronic circuits

Miodrag Potkonjak, Jeyavijayan Rajendran, Ramesh Karri, 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

Front-end-of-line attacks in split manufacturing

Jeyavijayan Rajendran, Jiang Hu, Yujie Wang, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

SLICED: Slide-based concurrent error detection technique for symmetric block ciphers

Jeyavijayan Rajendran, Ramesh Karri, Hetal Borad, 2010, 2010 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

Making split fabrication synergistically secure and manufacturable

Jeyavijayan Rajendran, Jiang Hu, Yujie Wang, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Security analysis of logic obfuscation

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2012, DAC Design Automation Conference 2012.

Side-Channel Attacks

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2020 .

Shielding Heterogeneous MPSoCs From Untrustworthy 3PIPs Through Security- Driven Task Scheduling

Jeyavijayan Rajendran, Ramesh Karri, Chen Liu, 2013, IEEE Transactions on Emerging Topics in Computing.

Hot topic session 9C: Test and fault tolerance for emerging memory technologies

Jeyavijayan Rajendran, Suriyaprakash Natarajan, Amitava Majumdar, 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction

Jeyavijayan Rajendran, Jiang Hu, N. G. Jayasankaran, 2022, IEEE Transactions on Emerging Topics in Computing.

NDR based threshold logic fabric with memristive synapses

Jeyavijayan Rajendran, Garrett S. Rose, Harika Manem, 2009, 2009 9th IEEE Conference on Nanotechnology (IEEE-NANO).

Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano Memristive Trainable Threshold Gate Array

Jeyavijayan Rajendran, Garrett S. Rose, Harika Manem, 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

Making split fabrication synergistically secure and manufacturable

Jeyavijayan Rajendran, Jiang Hu, Yujie Wang, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Hardware Trojan Attacks in FPGA and Protection Approaches

Jeyavijayan Rajendran, Vinayaka Jyothi, 2018 .

Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage

Jeyavijayan Rajendran, Ramesh Karri, Vivekananda Vedula, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).