Ozgur Sinanoglu

发表

Engineering crossbar based emerging memory technologies

Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

Embedded tutorial: Regaining hardware security and trust

Ozgur Sinanoglu, 2013, 2013 14th Latin American Test Workshop - LATW.

Test power reductions through computationally efficient, decoupled scan chain modifications

Ozgur Sinanoglu, Alex Orailoglu, 2005, IEEE Transactions on Reliability.

Post-SAT 3: Stripped-Functionality Logic Locking

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2020 .

A secure design-for-test infrastructure for lifetime security of SoCs

Ramesh Karri, Ozgur Sinanoglu, Subidh Ali, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

A New Paradigm in Split Manufacturing: Lock the FEOL, Unlock at the BEOL

Ozgur Sinanoglu, Abhrajit Sengupta, Mohammed Nabeel, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking pdf

Hai Zhou, Franco Stellari, Ujjwal Guin, 2020, ArXiv.

Rewind-Support for Peak Capture Power Reduction in Launch-Off-Shift Testing

Ozgur Sinanoglu, 2011, 2011 Asian Test Symposium.

AES design space exploration new line for scan attack resiliency

Ramesh Karri, Ozgur Sinanoglu, Subidh Ali, 2014, 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC).

Power-side-channel analysis of carbon nanotube FET based design

Ozgur Sinanoglu, Subidh Ali, Chandra K. H. Suresh, 2016, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS).

Guest Editorial Special Issue on Secure and Trustworthy Computing

Ramesh Karri, Ozgur Sinanoglu, 2016, JETC.

A novel scan architecture for power-efficient, rapid test [sequential circuits]

Ozgur Sinanoglu, Alex Orailoglu, 2002, IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002..

Add-on blocks and algorithms for improving stimulus compression

Ozgur Sinanoglu, Nader Alawadhi, Mohammed Al-Mulla, 2010, 2010 15th IEEE European Test Symposium.

ScanSAT: unlocking obfuscated scan chains

Ozgur Sinanoglu, Baker Mohammad, Hani H. Saleh, 2019, ASP-DAC.

Adaptive Generation of Unique IDs for Digital Chips through Analog Excitation

Ozgur Sinanoglu, Sule Ozev, Chandra K. H. Suresh, 2015, TODE.

Trustworthy Hardware Design: Combinational Logic Locking Techniques

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2020 .

A novel scan architecture for power-efficient, rapid test

Ozgur Sinanoglu, Alex Orailoglu, 2002, ICCAD 2002.

Error-resilient design of branch predictors for effective yield improvement

Ozgur Sinanoglu, Sobeeh Almukhaizim, O. Sinanoglu, 2011, 2011 12th Latin American Test Workshop (LATW).

Compaction schemes with minimum test application time

Ozgur Sinanoglu, Alex Orailoglu, 2001, Proceedings 10th Asian Test Symposium.

Pipelined test of SOC cores through test data transformations

Ozgur Sinanoglu, Alex Orailoglu, 2004, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004..

SMART: Secure Magnetoelectric AntifeRromagnet-Based Tamper-Proof Non-Volatile Memory

Ozgur Sinanoglu, Johann Knechtel, Nikhil Rangarajan, 2019, ArXiv.

Reconciling the Dichotomy Between Test and Security

Ramesh Karri, Ozgur Sinanoglu, Yiorgos Makris, 2013, ETS 2013.

The SAT Attack

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2020 .

X-Align: Improving the Scan Cell Observability of Response Compactors

Ozgur Sinanoglu, Sobeeh Almukhaizim, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Guest Editorial Special Section on Hardware Security and Trust

Ahmad-Reza Sadeghi, Ramesh Karri, Ozgur Sinanoglu, 2015, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

TMO: A new class of attack on cipher misusing test infrastructure

Ozgur Sinanoglu, Subidh Ali, 2015, 2015 IEEE 33rd VLSI Test Symposium (VTS).

Concerted wire lifting: Enabling secure and cost-effective split manufacturing

Ozgur Sinanoglu, Johann Knechtel, Satwik Patnaik, 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

On Improving the Security of Logic Locking

Ramesh Karri, Ozgur Sinanoglu, Muhammad Yasin, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Scan Architecture With Align-Encode

Ozgur Sinanoglu, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

X-alignment techniques for improving the observability of response compactors

Ozgur Sinanoglu, Sobeeh Almukhaizim, 2009, 2009 International Test Conference.

Design and analysis of ring oscillator based Design-for-Trust technique

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2011, 29th VLSI Test Symposium.

New scan-based attack using only the test mode

Ramesh Karri, Ozgur Sinanoglu, Subidh Ali, 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

Raise Your Game for Split Manufacturing: Restoring the True Functionality Through BEOL

Ozgur Sinanoglu, Johann Knechtel, Satwik Patnaik, 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

Proceedings of the 2017 ACM on Asia Conference on Computer and Communications Security

Ahmad-Reza Sadeghi, Ozgur Sinanoglu, Xun Yi, 2017, AsiaCCS.

GNNUnlock: Graph Neural Networks-based Oracle-less Unlocking Scheme for Provably Secure Logic Locking pdf

Faiq Khalid, Muhammad Abdullah Hanif, Ozgur Sinanoglu, 2020, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

An Interposer-Based Root of Trust: Seize the Opportunity for Secure System-Level Integration of Untrusted Chiplets pdf

Ozgur Sinanoglu, Mohammed Nabeel, Johann Knechtel, 2019, ArXiv.

Protect Your Chip Design Intellectual Property: An Overview

Ozgur Sinanoglu, Johann Knechtel, Satwik Patnaik, 2019, COINS.

What to Lock?: Functional and Parametric Locking

Jeyavijayan Rajendran, Ozgur Sinanoglu, Yiorgos Makris, 2017, ACM Great Lakes Symposium on VLSI.

Obfuscating the interconnects: Low-cost and resilient full-chip layout camouflaging

Ozgur Sinanoglu, Johann Knechtel, Satwik Patnaik, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Post-SAT 1: Point Function-Based Logic Locking

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2020 .

Dynamic test data transformations for average and peak power reductions

Ozgur Sinanoglu, Alex Orailoglu, I. Bayraktaroglu, 2002, Proceedings The Seventh IEEE European Test Workshop.

Adaptive testing: Conquering process variations

Ozgur Sinanoglu, Sule Ozev, Peter C. Maxwell, 2012, 2012 17th IEEE European Test Symposium (ETS).

Removal Attacks on Logic Locking and Camouflaging Techniques

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2020, IEEE Transactions on Emerging Topics in Computing.

XOR-Based Response Compactor Adaptive to X-Density Variation

Ozgur Sinanoglu, Samah Mohamed Saeed, 2010, 2010 19th IEEE Asian Test Symposium.

New Scan-Based Attack Using Only the Test Mode and an Input Corruption Countermeasure

Ramesh Karri, Ozgur Sinanoglu, Subidh Ali, 2013, VLSI-SoC.

Reducing Average and Peak Test Power Through Scan Chain Modification

Ozgur Sinanoglu, Alex Orailoglu, Ismet Bayraktaroglu, 2003, J. Electron. Test..

Revisiting Logic Locking for Reversible Computing

Ozgur Sinanoglu, Nimisha Limaye, Muhammad Yasin, 2019, 2019 IEEE European Test Symposium (ETS).

Low Cost Scan Test by Test Correlation Utilization

Ozgur Sinanoglu, 2007, Journal of Computer Science and Technology.

2012 JETTA Reviewers

Luigi Carro, Fernando Morgado Dias, Irith Pomeranz, 2013, J. Electron. Test..

Security analysis of Anti-SAT

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

Keynote: A Disquisition on Logic Locking

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Obfuscating the Interconnects: Low-Cost and Resilient Full-Chip Layout Camouflaging

Ozgur Sinanoglu, Johann Knechtel, Satwik Patnaik, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Security Assessment of Cyberphysical Digital Microfluidic Biochips

Mohamed Ibrahim, Ramesh Karri, Ozgur Sinanoglu, 2016, IEEE/ACM Transactions on Computational Biology and Bioinformatics.

Post-SAT 2: Insertion of SAT-Unresolvable Structures

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2020 .

Timing Attack and Countermeasure on NEMS Relay Based Design of Block Ciphers

Ozgur Sinanoglu, Samah Mohamed Saeed, Bodhisatwa Mazumdar, 2017, IEEE Transactions on Emerging Topics in Computing.

Adapting to Varying Distribution of Unknown Response Bits

Ozgur Sinanoglu, Sule Ozev, Chandra K. H. Suresh, 2016, TODE.

Regaining Trust in VLSI Design: Design-for-Trust Techniques

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2014, Proceedings of the IEEE.

Truly Stripping Functionality for Logic Locking: A Fault-Based Perspective

Ozgur Sinanoglu, Abhrajit Sengupta, Nimisha Limaye, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Multi-modal response compaction adaptive to x-density variation

Ozgur Sinanoglu, Samah Mohamed Saeed, 2012, IET Comput. Digit. Tech..

Testing the Trustworthiness of IC Testing: An Oracle-Less Attack on IC Camouflaging

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2017, IEEE Transactions on Information Forensics and Security.

Scan Chain Hold-Time Violations: Can They be Tolerated?

Ozgur Sinanoglu, Philip Schremmer, 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Adaptive Reduction of the Frequency Search Space for Multi- $V_{\mathrm{ dd}}$ Digital Circuits Using Variation Sensitive Ring Oscillators

Ozgur Sinanoglu, Sule Ozev, Chandra K. H. Suresh, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Isolation Techniques for Soft Cores

Tsvetomir Petrov, Ozgur Sinanoglu, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Towards provably-secure performance locking

Ozgur Sinanoglu, Yiorgos Makris, Abhrajit Sengupta, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Design Obfuscation versus Test

Ozgur Sinanoglu, Farimah Farahmandi, Ronald Blanton, 2020, 2020 IEEE European Test Symposium (ETS).

TTLock: Tenacious and Traceless Logic Locking: IEEE Hardware Oriented Security and Trust Conference (HOST)

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2007 .

A Comprehensive Design-for-Test Infrastructure in the Context of Security-Critical Applications

Ozgur Sinanoglu, Samah Mohamed Saeed, 2017, IEEE Design & Test.

Sneak-path Testing of Memristor-based Memories

Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, 2013, 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems.

Space and time compaction schemes for embedded cores

Ozgur Sinanoglu, Alex Orailoglu, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Fast and energy-frugal deterministic test through efficient compression and compaction techniques

Ozgur Sinanoglu, Alex Orailoglu, 2004, J. Syst. Archit..

Test Data Volume Comparison: Monolithic vs. Modular SoC Testing

Erik Jan Marinissen, Ozgur Sinanoglu, Jeff Rearick, 2009, IEEE Design & Test of Computers.

Hierarchical constraint conscious RT-level test generation

Ozgur Sinanoglu, Alex Orailoglu, 2003, Euromicro Symposium on Digital System Design, 2003. Proceedings..

Spin-Orbit Torque Devices for Hardware Security: From Deterministic to Probabilistic Regime

Ozgur Sinanoglu, Johann Knechtel, Nikhil Rangarajan, 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations

Ozgur Sinanoglu, 2008, J. Electron. Test..

CAS-Unlock: Unlocking CAS-Lock without Access to a Reverse-Engineered Netlist

Ozgur Sinanoglu, Abhrajit Sengupta, O. Sinanoglu, 2019, IACR Cryptol. ePrint Arch..

Predictive Techniques for Projecting Test Data Volume Compression

Ozgur Sinanoglu, Samah Mohamed Saeed, Sobeeh Almukhaizim, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design Flow for Active Interposer-Based 2.5-D ICs and Study of RISC-V Architecture With Secure NoC

Saibal Mukhopadhyay, Ozgur Sinanoglu, Madhavan Swaminathan, 2020, IEEE Transactions on Components, Packaging and Manufacturing Technology.

Aliasing-free Space and Time Compaction for Embedded Cores

Ozgur Sinanoglu, Alex Orailoglu, 2001 .

Partial Core Encryption for Performance-Efficient Test of SOCs

Ozgur Sinanoglu, Alex Orailoglu, 2003, ICCAD 2003.

A Disquisition on Logic Locking

Jeyavijayan Rajendran, Ozgur Sinanoglu, Michael Zuzak, 2019 .

The Need for Logic Locking

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2019, Analog Circuits and Signal Processing.

A unified on-chip transformation framework for cost-effective soc test

Ozgur Sinanoglu, Alex Orailoglu, 2004 .

Align-Encode Delay Assignment in the Case of XOR-Decompressors: Impact of Parallel Computations

Ozgur Sinanoglu, Nader Alawadhi, Mohammed Al-Mulla, 2009, J. Interconnect. Networks.

Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing

Ozgur Sinanoglu, Samah Mohamed Saeed, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

3D Integration: Another Dimension Toward Hardware Security

Ozgur Sinanoglu, Johann Knechtel, Satwik Patnaik, 2019, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS).

VLSI testing based security metric for IC camouflaging

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2013, 2013 IEEE International Test Conference (ITC).

Efficient Construction of Aliasing-Free Compaction Circuitry

Ozgur Sinanoglu, Alex Orailoglu, 2002, IEEE Micro.

Reconfigurable low-power Concurrent Error Detection in logic circuits

Ozgur Sinanoglu, Sobeeh Almukhaizim, Sara Bunian, 2010, 2010 5th International Design and Test Workshop.

Microfluidic encryption of on-chip biochemical assays

Mohamed Ibrahim, Ramesh Karri, Ozgur Sinanoglu, 2016, 2016 IEEE Biomedical Circuits and Systems Conference (BioCAS).

Timing attack on NEMS relay based design of AES

Ozgur Sinanoglu, Subidh Ali, Samah Mohamed Saeed, 2015, 2015 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

Security Promises and Vulnerabilities in Emerging Reconfigurable Nanotechnology-Based Circuits

Ozgur Sinanoglu, Johann Knechtel, Satwik Patnaik, 2022, IEEE Transactions on Emerging Topics in Computing.

Reconciling the IC test and security dichotomy

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2013, 2013 18th IEEE European Test Symposium (ETS).

Can assay outcomes of digital microfluidic biochips be manipulated

Ozgur Sinanoglu, Muhammad Ibrahim, Krishnendu Chakrabarty, 2015 .

Hardware Security and Trust: Logic Locking as a Design-for-Trust Solution

Jeyavijayan Rajendran, Ozgur Sinanoglu, Bodhisatwa Mazumdar, 2018, The IoT Physical Layer.

Scan to Nonscan Conversion via Test Cube Analysis

Ozgur Sinanoglu, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Toggle-Based Masking Scheme for Clustered Unknown Response Bits

Ozgur Sinanoglu, 2011, 2011 Sixteenth IEEE European Test Symposium.

CamoPerturb: Secure IC camouflaging for minterm protection

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Slack removal for enhanced reliability and trust

Ozgur Sinanoglu, Samah Mohamed Saeed, Abishek Ramdas, 2014, 2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Financial Implications of Security in VLSI Test

Ozgur Sinanoglu, 2010 .

Is Robust Design-for-Security Robust Enough? Attack on Locked Circuits with Restricted Scan Chain Access

Ozgur Sinanoglu, Abhrajit Sengupta, Mohammed Nabeel, 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Peak Power Reduction Through Dynamic Partitioning of Scan Chains

Ozgur Sinanoglu, Sobeeh Almukhaizim, 2008, 2008 IEEE International Test Conference.

Attacking Split Manufacturing from a Deep Learning Perspective

Evangeline F. Y. Young, Ozgur Sinanoglu, Haoyu Yang, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

TTLock: Tenacious and traceless logic locking

Ozgur Sinanoglu, Muhammad Yasin, Bodhisatwa Mazumdar, 2017, 2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

Sneak-Path Testing of Crossbar-Based Nonvolatile Random Access Memories

Sachhidh Kannan, Jeyavijayan Rajendran, Ramesh Karri, 2013, IEEE Transactions on Nanotechnology.

Piezo-PUF: Physical Unclonable Functions for Vacuum-Packaged, Piezoelectric MEMS

Ozgur Sinanoglu, Ibrahim Abe M. Elfadel, Alabi Bojesomo, 2019, 2019 Symposium on Design, Test, Integration & Packaging of MEMS and MOEMS (DTIP).

Autonomous yet deterministic test of SOC cores

Ozgur Sinanoglu, Alex Orailoglu, O. Sinanoglu, 2004, 2004 International Conferce on Test.

RT-level fault simulation based on symbolic propagation

Ozgur Sinanoglu, Alex Orailoglu, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

Fast and energy-frugal deterministic test through test vector correlation exploitation

Ozgur Sinanoglu, Alex Orailoglu, 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

Test data manipulation techniques for energy-frugal, rapid scan test

Ozgur Sinanoglu, Alex Orailoglu, 2003, 2003 Test Symposium.

Mixed-Signal Hardware Security Using MixLock: Demonstration in an Audio Application

Ozgur Sinanoglu, Hassan Aboushady, Julian Leonhard, 2019, 2019 16th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD).

Efficient RT-level fault diagnosis methodology

Ozgur Sinanoglu, Alex Orailoglu, 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

Identification of IR-drop hot-spots in defective power distribution network using TDF ATPG

Mark Mohammad Tehranipoor, Ozgur Sinanoglu, Junxia Ma, 2010, 2010 5th International Design and Test Workshop.

Leveraging Testing Tools for Protecting Design IP

Ozgur Sinanoglu, 2012, ITC 2012.

Scan attack on Elliptic Curve Cryptosystem

Ozgur Sinanoglu, Subidh Ali, 2015, 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

Test-mode-only scan attack using the boundary scan chain

Ramesh Karri, Ozgur Sinanoglu, Subidh Ali, 2014, 2014 19th IEEE European Test Symposium (ETS).

Test power reduction via deterministic alignment of stimulus and response bits

Ozgur Sinanoglu, Sobeeh Almukhaizim, Eman AlQuraishi, 2011, 2011 12th Latin American Test Workshop (LATW).

Scan Cell Positioning for Boosting the Compression of Fan-Out Networks

Ozgur Sinanoglu, Alex Orailoglu, Mohammed Al-Mulla, 2009, Journal of Computer Science and Technology.

DfT support for launch and capture power reduction in launch-off-capture testing

Ozgur Sinanoglu, Samah Mohamed Saeed, 2012, 2012 17th IEEE European Test Symposium (ETS).

Reconfigurable low-power Concurrent Error Detection in logic circuits

Ozgur Sinanoglu, Sobeeh Almukhaizim, Sara Bunian, 2010, IDT.

Expedited response compaction for scan power reduction

Ozgur Sinanoglu, Samah Mohamed Saeed, 2011, 29th VLSI Test Symposium.

Test-mode-only scan attack and countermeasure for contemporary scan architectures

Ramesh Karri, Ozgur Sinanoglu, Subidh Ali, 2014, 2014 International Test Conference.

Fault Model Independent, Maximal Compaction of Test Responses in the Presence of Unknown Response Bits

Ozgur Sinanoglu, 2012, Comput. J..

Improving the Effectiveness of Combinational Decompressors Through Judicious Partitioning of Scan Cells

Ozgur Sinanoglu, 2008, J. Electron. Test..

Raise your game for split manufacturing: restoring the true functionality through BEOL

Ozgur Sinanoglu, Johann Knechtel, Satwik Patnaik, 2018, DAC.

Guest Editors Introduction: Security of Beyond CMOS Devices: Issues and Opportunities

Ozgur Sinanoglu, Swarup Bhunia, An Chen, 2017, IEEE Trans. Emerg. Top. Comput..

Logic encryption: A fault analysis perspective

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Predictive analysis for projecting test compression levels

Ozgur Sinanoglu, Sobeeh Almukhaizim, O. Sinanoglu, 2010, 2010 IEEE International Test Conference.

H-Align: Improving the Scan Cell Observability of Horizontal Response Compactors

Ozgur Sinanoglu, Sobeeh Almukhaizim, 2009 .

Supply-Chain Security of Digital Microfluidic Biochips

Mohamed Ibrahim, Jeyavijayan Rajendran, Ozgur Sinanoglu, 2016, Computer.

Transforming between logic locking and IC camouflaging

Ozgur Sinanoglu, Muhammad Yasin, O. Sinanoglu, 2015, 2015 10th International Design & Test Symposium (IDT).

Security analysis of integrated circuit camouflaging

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2013, CCS.

A Compact Implementation of Salsa20 and Its Power Analysis Vulnerabilities

Ozgur Sinanoglu, Subidh Ali, Bodhisatwa Mazumdar, 2016, ACM Trans. Design Autom. Electr. Syst..

Fault Analysis-Based Logic Encryption

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2015, IEEE Transactions on Computers.

New scan attacks against state-of-the-art countermeasures and DFT

Ramesh Karri, Ozgur Sinanoglu, Subidh Ali, 2014, 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Ozgur Sinanoglu, Jens Lienig, Ibrahim M. Elfadel, 2017, IPSJ Trans. Syst. LSI Des. Methodol..

Fault Analysis-based Logic Encryption (Preprint)

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2013 .

Ultra-Low Power, Secure IoT Platform for Predicting Cardiovascular Diseases

Mohammed Ismail, Ozgur Sinanoglu, Baker Mohammad, 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

Advancing hardware security using polymorphic and stochastic spin-hall effect devices

Ozgur Sinanoglu, Johann Knechtel, Nikhil Rangarajan, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Sneak path testing and fault modeling for multilevel memristor-based memories

Sachhidh Kannan, Ramesh Karri, Ozgur Sinanoglu, 2013, 2013 IEEE 31st International Conference on Computer Design (ICCD).

Toward Physically Unclonable Functions From Plasmonics-Enhanced Silicon Disc Resonators

Ozgur Sinanoglu, Johann Knechtel, Mahmoud Rasras, 2019, Journal of Lightwave Technology.

Power Side-Channel Attacks in Negative Capacitance Transistor

Ozgur Sinanoglu, Jorg Henkel, Johann Knechtel, 2020, IEEE Micro.

Scan attack in presence of mode-reset countermeasure

Ramesh Karri, Ozgur Sinanoglu, Subidh Ali, 2013, 2013 IEEE 19th International On-Line Testing Symposium (IOLTS).

Efficient RT-level fault diagnosis methodology

Ozgur Sinanoglu, Alex Orailoglu, 2004 .

Activation of logic encrypted chips: Pre-test or post-test?

Jeyavijayan Rajendran, Ozgur Sinanoglu, Samah Mohamed Saeed, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Retiming scan circuit to eliminate timing penalty

Vishwani D. Agrawal, Ozgur Sinanoglu, 2012, 2012 13th Latin American Test Workshop (LATW).

Partial Core Encryption for Performance-Efficient Test of SOCs

Ozgur Sinanoglu, Alex Orailoglu, 2003, ICCAD.

Dynamic Scan Chain Partitioning for Reducing Peak Shift Power During Test

Ozgur Sinanoglu, Sobeeh Almukhaizim, 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

DynUnlock: Unlocking Scan Chains Obfuscated using Dynamic Keys

Ozgur Sinanoglu, Nimisha Limaye, O. Sinanoglu, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Reconfigurable Concurrent Error Detection Adaptive to Dynamicity of Power Constraints

Ozgur Sinanoglu, Sobeeh Almukhaizim, Sara Bunian, 2010, 2010 15th IEEE European Test Symposium.

An Inherently Stabilizing Algorithm for Node-To-Node Routing over All Shortest Node-Disjoint Paths in Hypercube Networks

Ozgur Sinanoglu, Mehmet Hakan Karaata, Bader F. AlBdaiwi, 2010, IEEE Transactions on Computers.

Eliminating the Timing Penalty of Scan

Vishwani D. Agrawal, Ozgur Sinanoglu, 2013, J. Electron. Test..

Adaptive reduction of the frequency search space for multi-vdd digital circuits

Ozgur Sinanoglu, Sule Ozev, Chandra K. H. Suresh, 2013, DATE.

Test power reduction through minimization of scan chain transitions

Ozgur Sinanoglu, Alex Orailoglu, Ismet Bayraktaroglu, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

Extending the applicability of parallel-serial scan designs

Ozgur Sinanoglu, Alex Orailoglu, Baris Arslan, 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

2.5D Root of Trust: Secure System-Level Integration of Untrusted Chiplets

Ozgur Sinanoglu, Johann Knechtel, Mohammed Nabeel, 2020, IEEE Transactions on Computers.

Reconfigurable Concurrent Error Detection adaptive to dynamicity of power constraints

Ozgur Sinanoglu, Sobeeh Almukhaizim, Sara Bunian, 2010, ETS.

Provably-Secure Logic Locking: From Theory To Practice

Jeyavijayan Rajendran, Ozgur Sinanoglu, Abhrajit Sengupta, 2017, CCS.

MAGIC: Malicious Aging in Circuits/Cores

Ramesh Karri, Ozgur Sinanoglu, Xueyang Wang, 2015, TACO.

Pattern Encodability Enhancements for Test Stimulus Decompressors

Ozgur Sinanoglu, Nader Alawadhi, Mohammed Al-Mulla, 2010, 2010 19th IEEE Asian Test Symposium.

Test access mechanism for chips with spare identical cores

Ozgur Sinanoglu, 2012, 2012 IEEE 18th International On-Line Testing Symposium (IOLTS).

Guest Editors Introduction: Special Section on Emerging Technologies in Computer Design

Ozgur Sinanoglu, Omer Khan, 2019, IEEE Trans. Emerg. Top. Comput..

Rethinking split manufacturing: An information-theoretic approach with secure layout techniques

Ozgur Sinanoglu, Siddharth Garg, Abhrajit Sengupta, 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Belling the CAD: Toward Security-Centric Electronic System Design

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Enhancing encoding capacity of combinational test stimulus decompressors

Ozgur Sinanoglu, Nader Alawadhi, Mohammed Al-Mulla, 2011, Science China Information Sciences.

Opening the Doors to Dynamic Camouflaging: Harnessing the Power of Polymorphic Devices pdf

Ramesh Karri, Ozgur Sinanoglu, Johann Knechtel, 2018, IEEE Transactions on Emerging Topics in Computing.

Towards Provably Secure Logic Locking for Hardening Hardware Security Dissertation Summary: IEEE TTTC E.J. McCluskey Doctoral Thesis Award Competition

Ozgur Sinanoglu, Muhammad Yasin, 2018, 2018 IEEE International Test Conference (ITC).

2015 JETTA Reviewers

Robert Wille, Yong-Bin Kim, Alexandre M. Amory, 2016, Journal of electronic testing.

Align-Encode with XOR-based decompressors

Ozgur Sinanoglu, Nader Alawadhi, Mohammed Almulla, 2009 .

Security Vulnerabilities of Emerging Nonvolatile Main Memories and Countermeasures

Sachhidh Kannan, Ramesh Karri, Ozgur Sinanoglu, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A distributed algorithm for XOR-Decompression with stimulus fragment move to reduce chip testing costs

Ozgur Sinanoglu, Mohammed Almulla, 2009 .

Novel hazard-free majority voter for n-modular redundancy-based fault tolerance in asynchronous circuits

Ozgur Sinanoglu, Sobeeh Almukhaizim, 2011, IET Comput. Digit. Tech..

Utilisation of inverse compatibility for test cost reductions

Ozgur Sinanoglu, Mohammed Al-Mulla, Mohammed Nael Taha, 2009, IET Comput. Digit. Tech..

SARLock: SAT attack resistant logic locking

Ozgur Sinanoglu, Muhammad Yasin, Bodhisatwa Mazumdar, 2016, 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

Stripped Functionality Logic Locking With Hamming Distance-Based Restore Unit (SFLL-hd) – Unlocked

Ozgur Sinanoglu, Ming Tang, Fangfei Yang, 2019, IEEE Transactions on Information Forensics and Security.

Evolution of logic locking

Ozgur Sinanoglu, Muhammad Yasin, O. Sinanoglu, 2017, 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

Is split manufacturing secure?

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Guest Editors' Introduction: Special Issue on Emerging Technologies in Computer Design

Ozgur Sinanoglu, Ümit Y. Ogras, 2020, IEEE Trans. Emerg. Top. Comput..

Security implications of cyberphysical digital microfluidic biochips

Mohamed Ibrahim, Ramesh Karri, Ozgur Sinanoglu, 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).

Revival of partial scan: Test cube analysis driven conversion of flip-flops

Ozgur Sinanoglu, Nader Alawadhi, 2011, 29th VLSI Test Symposium.

Scan Design: Basics, Advancements, and Vulnerabilities

Ozgur Sinanoglu, Samah Mohamed Saeed, Sk Subidh Ali, 2017 .

Aggressive test power reduction through test stimuli transformation

Ozgur Sinanoglu, Alex Orailoglu, 2003, Proceedings 21st International Conference on Computer Design.

A Comparative Security Analysis of Current and Emerging Technologies

Ozgur Sinanoglu, Subidh Ali, Chandra K. H. Suresh, 2016, IEEE Micro.

UNSAIL: Thwarting Oracle-Less Machine Learning Attacks on Logic Locking pdf

Ozgur Sinanoglu, Baker Mohammad, Mahmoud Al-Qutayri, 2020, IEEE Transactions on Information Forensics and Security.

Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach

Ramesh Karri, Ozgur Sinanoglu, Jeyavijayan J. V. Rajendran, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Parity-based output compaction for core-based SOCs [logic testing]

Ozgur Sinanoglu, Alex Orailoglu, 2003, The Eighth IEEE European Test Workshop, 2003. Proceedings..

Test power reduction via deterministic alignment of stimulus and response bits

Ozgur Sinanoglu, Sobeeh Almukhaizim, Eman AlQuraishi, 2011 .

An Optimal Inherently Stabilizing 2-Neighborhood Crash Resilient Protocol for Secure and Reliable Routing in Hypercube Networks

Ozgur Sinanoglu, Mehmet Hakan Karaata, Bader F. AlBdaiwi, 2012, Comput. J..

Analysis of The Test Data Volume Reduction Benefit of Modular SOC Testing

Erik Jan Marinissen, Ozgur Sinanoglu, 2008, 2008 Design, Automation and Test in Europe.

On mitigation of side-channel attacks in 3D ICs: Decorrelating thermal patterns from power and activity

Ozgur Sinanoglu, Johann Knechtel, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

A Brief History of Logic Locking

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2020 .

Application of serial transformations in scan-based SOC test for test cost reduction

Ozgur Sinanoglu, Alex Orailoglu, 2009 .

Thwarting All Logic Locking Attacks: Dishonest Oracle With Truly Random Logic Locking

Irene G. Karybali, Ozgur Sinanoglu, Nimisha Limaye, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Adaptive testing of chips with varying distributions of unknown response bits

Ozgur Sinanoglu, Sule Ozev, Chandra K. H. Suresh, 2012, 2012 17th IEEE European Test Symposium (ETS).

Do you trust your chip?

Ozgur Sinanoglu, 2016, 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS).

Diagnosis, Modeling and Tolerance of Scan Chain Hold-Time Violations

Ozgur Sinanoglu, Philip Schremmer, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Construction of an adaptive scan network for test time and data volume reduction

Ozgur Sinanoglu, 2008, IET Comput. Digit. Tech..

Compacting test responses for deeply embedded SoC cores

Ozgur Sinanoglu, Alex Orailoglu, O. Sinanoglu, 2003, IEEE Design & Test of Computers.

A Non-Intrusive Isolation Approach for Soft Cores

Tsvetomir Petrov, Ozgur Sinanoglu, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

Approximating the age of RF/analog circuits through re-characterization and statistical estimation

Ramesh Karri, Ozgur Sinanoglu, Sule Ozev, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

MixLock: Securing Mixed-Signal Circuits via Logic Locking

Ozgur Sinanoglu, Haralampos-G. D. Stratigopoulos, Muhammad Yasin, 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A Modern Approach to IP Protection and Trojan Prevention: Split Manufacturing for 3D ICs and Obfuscation of Vertical Interconnects pdf

Ozgur Sinanoglu, Johann Knechtel, Satwik Patnaik, 2019, ArXiv.

Modeling scan chain modifications for scan-in test power minimization

Ozgur Sinanoglu, Alex Orailoglu, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

ATPG-based cost-effective, secure logic locking

Ozgur Sinanoglu, Abhrajit Sengupta, Muhammad Yasin, 2018, 2018 IEEE 36th VLSI Test Symposium (VTS).

Align-Encode: Improving the Encoding Capability of Test Stimulus Decompressors

Ozgur Sinanoglu, 2008, 2008 IEEE International Test Conference.

Tutorial 1

Ramesh Karri, Ozgur Sinanoglu, Peilin Song, 2006, 2006 Proceedings of the First Mobile Computing and Wireless Communication International Conference.

Customized Locking of IP Blocks on a Multi-Million-Gate SoC

Ozgur Sinanoglu, Abhrajit Sengupta, Mohammed Ashraf, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Testing Chips With Spare Identical Cores

Ozgur Sinanoglu, Abishek Ramdas, O. Sinanoglu, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Scan power reduction through test data transition frequency analysis

Ozgur Sinanoglu, Alex Orailoglu, Ismet Bayraktaroglu, 2002, Proceedings. International Test Conference.

Security analysis of logic encryption against the most effective side-channel attack: DPA

Ozgur Sinanoglu, Subidh Ali, Muhammad Yasin, 2015, 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

Physical Unclonable Functions and Intellectual Property Protection Techniques

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2017 .

Detection, diagnosis, and repair of faults in memristor-based memories

Sachhidh Kannan, Ramesh Karri, Ozgur Sinanoglu, 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

Novel Test-Mode-Only Scan Attack and Countermeasure for Compression-Based Scan Architectures

Ramesh Karri, Ozgur Sinanoglu, Subidh Ali, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Thwarting timing attacks on NEMS relay based designs

Ozgur Sinanoglu, Subidh Ali, Samah Mohamed Saeed, 2016, 2016 IEEE 34th VLSI Test Symposium (VTS).

High-level synthesis for security and trust

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2013, 2013 IEEE 19th International On-Line Testing Symposium (IOLTS).

Modeling, Detection, and Diagnosis of Faults in Multilevel Memristor Memories

Sachhidh Kannan, Ramesh Karri, Ozgur Sinanoglu, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Pre-SAT Logic Locking

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2020 .

Security analysis of logic obfuscation

Jeyavijayan Rajendran, Ramesh Karri, Ozgur Sinanoglu, 2012, DAC Design Automation Conference 2012.

Expedited-compact architecture for average scan power reduction

Ozgur Sinanoglu, Samah Mohamed Saeed, 2013, IEEE Design & Test.

Side-Channel Attacks

Jeyavijayan Rajendran, Ozgur Sinanoglu, Muhammad Yasin, 2020 .

Scan power minimization through stimulus and response transformations

Ozgur Sinanoglu, Alex Orailoglu, 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

On the Application of Dynamic Scan Chain Partitioning for Reducing Peak Shift Power

Ozgur Sinanoglu, Sobeeh Almukhaizim, Shouq Alsubaihi, 2010, J. Electron. Test..

Best of Both Worlds: Integration of Split Manufacturing and Camouflaging into a Security-Driven CAD Flow for 3D ICs

Ozgur Sinanoglu, Johann Knechtel, Satwik Patnaik, 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Secure memristor-based main memory

Sachhidh Kannan, Ozgur Sinanoglu, Naghmeh Karimi, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

Logic Locking With Provable Security Against Power Analysis Attacks

Ozgur Sinanoglu, Abhrajit Sengupta, Muhammad Yasin, 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Design and Analysis of an Adaptive X-Tolerant XOR Compactor with Controllable Fan-out

Ozgur Sinanoglu, Samah Mohamed Saeed, 2010 .

Logic Locking of Boolean Circuits: Provable Hardware-Based Obfuscation from a Tamper-Proof Memory

Giovanni Di Crescenzo, Ozgur Sinanoglu, Abhrajit Sengupta, 2019, SECITC.

Unified 2-D X-Alignment for Improving the Observability of Response Compactors

Ozgur Sinanoglu, Sobeeh Almukhaizim, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A Secure Design-for-Test Architecture to Thwart Attacks Throughout The Life Cycle of SoCs

Ramesh Karri, Ozgur Sinanoglu, Subidh Ali, 2015, ISCAS 2015.

Efficient RT-Level Fault Diagnosis

Ozgur Sinanoglu, Alex Orailoglu, 2005, Journal of Computer Science and Technology.

Improving the Effectiveness of XOR-based Decompressors through Horizontal/Vertical Move of Stimulus Fragments

Ozgur Sinanoglu, Nader Alawadhi, 2009, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Eliminating Performance Penalty of Scan

Ozgur Sinanoglu, 2012, 2012 25th International Conference on VLSI Design.

Power analysis attacks on ARX: An application to Salsa20

Ozgur Sinanoglu, Subidh Ali, Bodhisatwa Mazumdar, 2015, 2015 IEEE 21st International On-Line Testing Symposium (IOLTS).

ScanSAT: Unlocking Static and Dynamic Scan Obfuscation pdf

Ozgur Sinanoglu, Baker Mohammad, Hani H. Saleh, 2019, IEEE Transactions on Emerging Topics in Computing.

MuxLink: Circumventing Learning-Resilient MUX-Locking Using Graph Neural Network-based Link Prediction pdf

Ozgur Sinanoglu, Lilas Alrahis, Satwik Patnaik, 2021, 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Fa-SAT: Fault-aided SAT-based Attack on Compound Logic Locking Techniques

Ozgur Sinanoglu, Nimisha Limaye, Satwik Patnaik, 2021, 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE).

UNTANGLE: Unlocking Routing and Logic Obfuscation Using Graph Neural Networks-based Link Prediction

Muhammad Abdullah Hanif, Ozgur Sinanoglu, Lilas Alrahis, 2021, 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

AntiDOTE: Protecting Debug Against Outsourced Test Entities

Ozgur Sinanoglu, Mohammed Nabeel, Nimisha Limaye, 2022, IEEE Transactions on Emerging Topics in Computing.

Interposer-Based Root of Trust pdf

Ozgur Sinanoglu, Paul Gratz, Johann Knechtel, 2021, ArXiv.

Deep Learning Analysis for Split-Manufactured Layouts With Routing Perturbation

Evangeline F. Y. Young, Ozgur Sinanoglu, Johann Knechtel, 2021, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Guest Editorial: Special Issue On Emerging Technologies in Computer Design

Ozgur Sinanoglu, Ümit Y. Ogras, 2021, IEEE Trans. Emerg. Top. Comput..

Fortifying RTL Locking Against Oracle-Less (Untrusted Foundry) and Oracle-Guided Attacks

Ramesh Karri, Ozgur Sinanoglu, Siddharth Garg, 2021, 2021 58th ACM/IEEE Design Automation Conference (DAC).

Coherence Attacks and Countermeasures in Interposer-Based Systems

Ozgur Sinanoglu, Paul Gratz, Johann Knechtel, 2021, 2105.02917.

Breaking CAS-Lock and Its Variants by Exploiting Structural Traces

Ozgur Sinanoglu, Abhrajit Sengupta, Nimisha Limaye, 2021, IACR Cryptol. ePrint Arch..

Security Closure of Physical Layouts ICCAD Special Session Paper

Ramesh Karri, Ozgur Sinanoglu, Johann Knechtel, 2021, 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

Concerted Wire Lifting: Enabling Secure and Cost-Effective Split Manufacturing

Ozgur Sinanoglu, Johann Knechtel, Satwik Patnaik, 2022, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

GNNUnlock+: A Systematic Methodology for Designing Graph Neural Networks-Based Oracle-Less Unlocking Schemes for Provably Secure Logic Locking

Muhammad Abdullah Hanif, Ozgur Sinanoglu, Hani Saleh, 2022, IEEE Transactions on Emerging Topics in Computing.

GNN-RE: Graph Neural Networks for Reverse Engineering of Gate-Level Netlists

Ozgur Sinanoglu, Baker Mohammad, Mahmoud Al-Qutayri, 2022, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

PolyWorm: Leveraging Polymorphic Behavior to Implant Hardware Trojans

Ozgur Sinanoglu, Nimisha Limaye, Nikhil Rangarajan, 2021, IEEE Transactions on Emerging Topics in Computing.

Toward Security Closure in the Face of Reliability Effects ICCAD Special Session Paper

Ozgur Sinanoglu, Jens Lienig, Mohammed Nabeel, 2021, 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

OMLA: An Oracle-Less Machine Learning-Based Attack on Logic Locking

Ozgur Sinanoglu, Lilas Alrahis, Satwik Patnaik, 2022, IEEE Transactions on Circuits and Systems II: Express Briefs.