Johannes Zeppenfeld

发表

Autonomic Workload Management for Multi-core Processor Systems

Andreas Herkersdorf, Johannes Zeppenfeld, 2010, ARCS.

Walter Stechele, Andreas Herkersdorf, Thomas Sommer, 2009 .

Power Estimation of Time Variant SoCs with TAPES

Andreas Lankes, Thomas Wild, Johannes Zeppenfeld, 2007, 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007).

Organic Computing at the System on Chip Level

Wolfgang Rosenstiel, Walter Stechele, Oliver Bringmann, 2006, 2006 IFIP International Conference on Very Large Scale Integration.

An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors

Walter Stechele, Andreas Herkersdorf, Johannes Zeppenfeld, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

Combining Software and Hardware LCS for Lightweight On-Chip Learning

Wolfgang Rosenstiel, Oliver Bringmann, Andreas Herkersdorf, 2010, DIPES/BICC.

Hardware-Supported Learning Classifier Tables in Autonomic Systems on Chip

Walter Stechele, Andreas Herkersdorf, Johannes Zeppenfeld, 2008 .

Concepts for Autonomic Integrated Systems

Norbert Wehn, Jürgen Teich, Walter Stechele, 2007 .

Power Estimation of Time Variant SoCs with TAPES

Andreas Lankes, Johannes Zeppenfeld, Thomas Wild, 2007 .

Multi-Bit Error Protection for Self-Correcting CPU Pipelines

Walter Stechele, Andreas Herkersdorf, Johannes Zeppenfeld, 2009 .

Applying autonomic principles for workload management in multi-core systems on chip

Andreas Herkersdorf, Johannes Zeppenfeld, 2011, ICAC '11.

Autonomic MPSoCs for Reliable Systems

Norbert Wehn, Jürgen Teich, Walter Stechele, 2007 .

Hardware Support to Exploit Parallelism in Homogeneous and Heterogeneous Multi-Core Systems on Chip

Michael Meitinger, Andreas Herkersdorf, Andreas Lankes, 2010 .

Applying ASoC to Multi-core Applications for Workload Management

Wolfgang Rosenstiel, Walter Stechele, Oliver Bringmann, 2011, Organic Computing.

Hardware Support for Efficient Resource Utilization in Manycore Processor Systems

Michael Meitinger, Andreas Herkersdorf, Andreas Lankes, 2011, Multiprocessor System-on-Chip.

A rapid prototyping system for error-resilient multi-processor systems-on-chip

Norbert Wehn, Jürgen Teich, Walter Stechele, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

A low-overhead monitoring ring interconnect for MPSoC parameter optimization

Walter Stechele, Andreas Herkersdorf, Johannes Zeppenfeld, 2012, 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Using Partial-Run-Time Reconfigurable Hardware to accelerate Video Processing in Driver Assistance System

Walter Stechele, Johannes Zeppenfeld, Christopher Claus, 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration

Walter Stechele, Johannes Zeppenfeld, Christopher Claus, 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

System Level Simulation of Autonomic SoCs with TAPES

Andreas Lankes, Thomas Wild, Johannes Zeppenfeld, 2008, ARCS.

Combining Software and Hardware LCS for Lightweight On-chip Learning

Wolfgang Rosenstiel, Oliver Bringmann, Andreas Herkersdorf, 2011, Organic Computing.

Learning Classifier Tables for Autonomic Systems on Chip

Walter Stechele, Andreas Herkersdorf, Johannes Zeppenfeld, 2008, GI Jahrestagung.

Towards Scalability and Reliability of Autonomic Systems on Chip

Walter Stechele, Andreas Herkersdorf, Johannes Zeppenfeld, 2010, 2010 13th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing Workshops.

Autonomic System on Chip Platform

Wolfgang Rosenstiel, Walter Stechele, Oliver Bringmann, 2011, Organic Computing.