I-Chyn Wey

发表

Low-Voltage Low-Power Pipelined Input Subsampled Replica Algorithmic Noise-Tolerant Motion Estimation Circuit Design

I-Chyn Wey, Zhe-Yu Lin, Yu-Jie Tian, 2013 .

A 3.3 V 1 GHz high speed pipelined Booth multiplier

Hwang-Cherng Chow, I-Chyn Wey, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

A high-speed, high fan-in dynamic comparator with low transistor count

Hwang-Cherng Chow, I-Chyn Wey, Tz-Cheng He, 2014 .

Dynamic Channel Flow Control of Networks-on-Chip Systems for High Buffer Efficiency

An-Yeu Wu, I-Chyn Wey, Chih-Hao Chao, 2007, 2007 IEEE Workshop on Signal Processing Systems.

Low-power design towards implantable neural signal processor- energy efficiency analysis for near-threshold voltage circuits design

Cihun-Siyong Alex Gong, I-Chyn Wey, Shiang-Wei Li, 2015, 2015 International Symposium on Bioelectronics and Bioinformatics (ISBB).

High speed pipelined Booth multiplier for DSP applications

Hwang-Cherng Chow, I-Chyn Wey, 2005 .

A clock-fault tolerant architecture and circuit for reliable nanoelectronics system

Jie Chen, An-Yeu Wu, Jilin Liu, 2007, 2007 International Conference on Design & Technology of Integrated Systems in Nanoscale Era.

Near-threshold-voltage circuit design: The design challenges and chances

I-Chyn Wey, Chien-Chang Peng, Po-Jen Lin, 2014, 2014 International SoC Design Conference (ISOCC).

A portable all-digital pulsewidth control loop for SOC applications

Wei Wang, Chia-Tsun Wu, An-Yeu Wu, 2006, 2006 IEEE International Symposium on Circuits and Systems.

A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder

Hwang-Cherng Chow, I-Chyn Wey, 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

Reliable ultra-low-voltage low-power probabilistic-based noise-tolerant latch design

I-Chyn Wey, Chien-Chang Peng, Yi-Jung Lan, 2013, Microelectron. Reliab..

Reliable and low error dual modular redundancy FIR filter with wide protection window

I-Chyn Wey, Chien-Chang Peng, Heng-Jui Chou, 2014, IEICE Electron. Express.

Analysis of various body bias under near-threshold-voltage CMOS circuits

I-Chyn Wey, Jing-Yi Huang, 2017, 2017 International Conference on Applied System Innovation (ICASI).

ANewNoise-Tolerant DynamicCircuit Design withEnhanced PDP Performance underLowSNREnvironment

I-Chyn Wey, You-Gang Chen, 2006 .

Wide bandwidth and high precision power supply noise detector by using dual peak detection sample and hold circuits

Hwang-Cherng Chow, I-Chyn Wey, Chien-Chang Peng, 2014, Int. J. Circuit Theory Appl..

Power management design for lab-on-chip biosensors

Kambiz Moez, Jie Chen, I-Chyn Wey, 2016, 2016 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC).

Soft-Event-Upset and Soft-Event-Transient Tolerant CMOS Circuit Design for Low-Voltage Low-Power Wireless IoT Applications

I-Chyn Wey, Chun-Han Chen, Heng-Jui Chou, 2019, 2019 Eleventh International Conference on Ubiquitous and Future Networks (ICUFN).

A New Noise-Tolerant Dynamic Circuit Design with Enhanced PDP Performance under Low SNR Environment

I-Chyn Wey, You-Gang Chen, A. An-Yeu Wu, 2006, 2006 IEEE Asian Solid-State Circuits Conference.

All digital folded low‐area, low‐power maximum power point tracking chip for photovoltaic energy conversion system

I-Chyn Wey, Shu-Hao Kuo, Shu-Hao Kuo, 2014, Int. J. Circuit Theory Appl..

Hardware-efficient common-feedback Markov-random-field probabilistic-based noise-tolerant VLSI circuits

I-Chyn Wey, Ye-Jhih Shen, I-Chyn Wey, 2014, Integr..

A Fully Integrated Multistage Cross-Coupled Voltage Multiplier With No Reversion Power Loss in a Standard CMOS Process

Mohamad Sawan, Kambiz Moez, Jie Chen, 2017, IEEE Transactions on Circuits and Systems II: Express Briefs.

Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits

An-Yeu Wu, I-Chyn Wey, You-Gang Chen, 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design and control of a 10kw three-phase grid-tied back to back inverter

Woei-Luen Chen, I-Chyn Wey, Chun-Yuan Chen, 2017, 2017 15th International Conference on Quality in Research (QiR) : International Symposium on Electrical and Computer Engineering.

A fast and power-saving self-timed Manchester carry-bypass adder for Booth multiplier-accumulator design

Hwang-Cherng Chow, I-Chyn Wey, You-Gang Chen, 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.

Miniaturized UAV datalink frequency source system design

Hui Cao, I-Chyn Wey, Yu Qu, 2017, 2017 IEEE International Conference on Consumer Electronics - Taiwan (ICCE-TW).

Noise‐tolerant dynamic CMOS circuits design by using true single‐phase clock latching technique

I-Chyn Wey, Chun-Wei Chang, Yu-Cheng Liao, 2015, Int. J. Circuit Theory Appl..

Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits

An-Yeu Wu, Jie Chen, Changhong Yu, 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

Low-Power Noise-Immune Nanoscale Circuit Design Using Coding-Based Partial MRF Method

Xuan Zeng, Jianhao Hu, Yufeng Li, 2018, IEEE Journal of Solid-State Circuits.

The discrete-time model of the small signal compensator of the buck converter

I-Chyn Wey, Zhi-Qun Cheng, Xin-Xiang Lian, 2014, 2014 IEEE International Conference on Communiction Problem-solving.

Robust C-element design for soft-error mitigation

Changhong Yu, Cihun-Siyong Alex Gong, I-Chyn Wey, 2015, IEICE Electron. Express.

A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design

Yu-Sheng Yang, I-Chyn Wey, Chien-Chang Peng, 2014, Microelectron. J..

A Precise Power Supply Noise Detector with High- Linearity

I-Chyn Wey, Chien-Chang Peng, Yu-Jiang Liao, 2011 .

Noise-Tolerate Circuit Design and Implementation with28.7dB Noise-Immunity Improvement

Changhong Yu, I-Chyn Wey, You-Gang Chen, 2006 .

A low voltage instrumentation amplifier for sensor applications

Hwang-Cherng Chow, I-Chyn Wey, Hsin-Ti Chou, 2014, 2014 International SoC Design Conference (ISOCC).

An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on belief propagation

An-Yeu Wu, Jie Chen, I-Chyn Wey, 2008, 2008 IEEE International Symposium on Circuits and Systems.

A high speed scalable shift-register based on-chip serial communication design for SoC applications

Chia-Tsun Wu, An-Yeu Wu, Wei Wang, 2005, Research in Microelectronics and Electronics, 2005 PhD.

A 0.13μm hardware-efficient probabilistic-based noise-tolerant circuit design and implementation with 24.5dB noise-immunity improvement

Jie Chen, I-Chyn Wey, Changhong Yu, 2007, 2007 IEEE Asian Solid-State Circuits Conference.

Dynamic-static hybrid near-threshold-voltage adder design for ultra-low power applications

I-Chyn Wey, Chien-Chang Peng, Zhi-Qun Cheng, 2015, IEICE Electron. Express.

Parallel Balanced-Bit-Serial Design Technique for Ultra-Low-Voltage Circuits With Energy Saving and Area Efficiency Enhancement

I-Chyn Wey, Bing-Chen Wu, Bing-Chen Wu, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

Design and implementation of a voltage-controlled oscillator for MICS-based sensor network system

Yu-Lin Tsou, Changhong Yu, Cihun-Siyong Alex Gong, 2016 .

Reliable Low-Power Multiplier Design Using Fixed-Width Replica Redundancy Block

I-Chyn Wey, Chien-Chang Peng, Feng-Yu Liao, 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time

Wei Wang, Chia-Tsun Wu, An-Yeu Wu, 2006, 2006 IEEE International Symposium on Circuits and Systems.

Low-Error and Hardware-Efficient Fixed-Width Multiplier by Using the Dual-Group Minor Input Correction Vector to Lower Input Correction Vector Compensation Error

I-Chyn Wey, Chun-Chien Wang, 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Improved Low-Power Cost-Effective DCT Implementation Based on Markov Random Field and Stochastic Logic

Yan Li, I-Chyn Wey, Fan Yang, 2020, IEEE Transactions on Circuits and Systems for Video Technology.

Fast predictive motion estimation algorithm with adaptive search mode based on motion type classification

Lili Lin, I-Chyn Wey, Jing-Hua Ding, 2014, Signal, Image and Video Processing.

A 0.18=μm Probabilistic-Based Noise-Tolerate Circuit Design and Implementation with 28.7dB Noise-Immunity Improvement

An-Yeu Wu, Jie Chen, I-Chyn Wey, 2006, 2006 IEEE Asian Solid-State Circuits Conference.

Soft-error tolerant design in near-threshold-voltage computing

I-Chyn Wey, Heng-Jui Chou, Si-Zhan Fang, 2018, 2018 IEEE International Conference on Applied System Invention (ICASI).

An Area-Efficient Carry Select Adder Design by Sharing the Common Boolean Logic Term

I-Chyn Wey, Chien-Chang Peng, Yi-Sheng Lin, 2012 .

A wide-range and fast-locking frequency synthesizer for Wimax and WLAN applications

Chao-Chyun Chen, I-Chyn Wey, Chi-Nan Chuang, 2014, 2014 IEEE 3rd Global Conference on Consumer Electronics (GCCE).

A new low-voltage CMOS 1-bit full adder for high performance applications

Hwang-Cherng Chow, I-Chyn Wey, Chun-Hua Huang, 2002, Proceedings. IEEE Asia-Pacific Conference on ASIC,.

Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design

Hong Zhao, An-Yeu Wu, Jie Chen, 2007, 2007 IEEE International Symposium on Circuits and Systems.

A scalable DCO design for portable ADPLL designs

Wei Wang, Chia-Tsun Wu, An-Yeu Wu, 2005, 2005 IEEE International Symposium on Circuits and Systems.

A FREQUENCY ESTIMATIONALGORITHM FOR ADPLL DESIGNSWITH TWO-CYCLE LOCK-INTIME

Chia-Tsun Wu, I-Chyn Wey, 2006 .

A 2Gb/s high-speed scalable shift-register based on-chip serial communication design for SoC applications

An-Yeu Wu, I-Chyn Wey, Shih-Hung Chang, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Switching-energy reduction technique in SAR ADC for biomedical electronics

I-Chyn Wey, Xingyuan Tong, Yang Zhang, 2015 .

Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP Modules

An-Yeu Wu, I-Chyn Wey, You-Gang Chen, 2007, 2007 IEEE International Symposium on Circuits and Systems.

Low-error and area-efficient fixed-width multiplier by using minor input correction vector

I-Chyn Wey, Chun-Chien Wang, 2010, 2010 International Conference on Electronics and Information Engineering.