Adit D. Singh

发表

A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI)

Haihua Yan, Adit D. Singh, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Methodology for Identifying High Timing Variability Paths in Complex Designs

Adit D. Singh, Kewal K. Saluja, Virendra Singh, 2015, 2015 IEEE 24th Asian Test Symposium (ATS).

IC reliability simulator ARET and its application in design-for-reliability

Abhijit Chatterjee, Adit D. Singh, Xiangdong Xuan, 2003, 2003 Test Symposium.

Adaptive Unanimous Voting (UV) Scheme for Distributed Self-Diagnosis

Hee Yong Youn, Jae Young Lee, Adit D. Singh, 1995, IEEE Trans. Computers.

A random access scans architecture to reduce hardware overhead

Vishwani D. Agrawal, Adit D. Singh, Anand S. Mudlapur, 2005, IEEE International Conference on Test, 2005..

On optimizing VLSI testing for product quality using die-yield prediction

Adit D. Singh, C. Mani Krishna, 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

An IDDQ sensor for concurrent timing error detection

Adit D. Singh, Victor P. Nelson, C. G. Knight, 1998 .

On the Effect of Defect Clustering on Test Transparency and IC Test Optimization

Adit D. Singh, C. Mani Krishna, 1996, IEEE Trans. Computers.

Embedded Tutorial ET1: Better-than-Worst-Case Timing Designs

Adit D. Singh, 2015, 2015 28th International Conference on VLSI Design.

Timing Evaluation Tests for Scan Enable Signals with Application to TDF Testing

Adit D. Singh, Jie Zou, Chao Han, 2014, 2014 IEEE 23rd Asian Test Symposium.

A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging

Adit D. Singh, Kewal K. Saluja, Virendra Singh, 2017, J. Electron. Test..

SEU tolerant robust memory cell design

Masahiro Fujita, Adit D. Singh, Virendra Singh, 2012, 2012 IEEE 18th International On-Line Testing Symposium (IOLTS).

Evaluating the effectiveness of detecting delay defects in the slack interval: a simulation study

Haihua Yan, Adit D. Singh, 2004, 2004 International Conferce on Test.

Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Statistical estimation of correlated leakage power variation and its application to leakage-aware design

Abhijit Chatterjee, Adit D. Singh, Vivek De, 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

Should nanometer circuits be periodically tested in the field?

Adit D. Singh, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

On Minimization of Test Application Time for RAS

Hideo Fujiwara, Adit D. Singh, Kewal K. Saluja, 2010, 2010 23rd International Conference on VLSI Design.

An experimental evaluation of the differential BICS for I/sub DDQ/ testing

Adit D. Singh, Walter W. Weber, 1995, Proceedings 13th IEEE VLSI Test Symposium.

Binning for IC quality: experimental studies on the SEMATECH data

Adit D. Singh, Phil Nigh, Gaurav Sinha, 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

An output compression scheme for handling X-states from over-clocked delay tests

Adit D. Singh, Chao Han, Xi Qian, 2010, 2010 28th VLSI Test Symposium (VTS).

Distinguishing Resistive Small Delay Defects from Random Parameter Variations

Adit D. Singh, Xi Qian, 2010, 2010 19th IEEE Asian Test Symposium.

Detection conditions for errors in self-adaptive better-than-worst-case designs

Adit D. Singh, Ilia Polian, Jie Jiang, 2014, 2014 19th IEEE European Test Symposium (ETS).

Special session: Hot topics: Statistical test methods

Adit D. Singh, Florence Azaïs, Manuel J. Barragan Asian, 2015, 2015 IEEE 33rd VLSI Test Symposium (VTS).

Efficient partial enhanced scan for high coverage delay testing

Adit D. Singh, Chao Han, Virendra Singh, 2011, 2011 IEEE 43rd Southeastern Symposium on System Theory.

Screening for known good die (KGD) based on defect clustering: an experimental study

Adit D. Singh, C. Mani Krishna, Phil Nigh, 1997, Proceedings International Test Conference 1997.

Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing

Adit D. Singh, Gefu Xu, 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

Combining negative binomial and Weibull distributions for yield and reliability prediction

Adit D. Singh, Matt Grady, Kathleen G. Purdy, 2006, IEEE Design & Test of Computers.

Current testing: Dead or alive?

Adit D. Singh, Chintan Patel, Davide Appello, 2013, 2013 18th IEEE European Test Symposium (ETS).

Distributed Comparison Test Driven Multiprocessor Speed-Tuning: Targeting Performance Gains under Extreme Process Variations

Abhijit Chatterjee, Adit D. Singh, Joshua W. Wells, 2011, 2011 Asian Test Symposium.

Analysis and optimization of nanometer CMOS circuits for soft-error tolerance

Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Low-power domino circuits using NMOS pull-up on off-critical paths

Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril, 2005, ASP-DAC.

Improving CMOS open defect coverage using hazard activated tests

Adit D. Singh, Chao Han, 2014, 2014 IEEE 32nd VLSI Test Symposium (VTS).

Modified Scan Flip-Flop for Low Power Testing

Adit D. Singh, Sreejit Chakravarty, Virendra Singh, 2010, 2010 19th IEEE Asian Test Symposium.

Extending integrated-circuit yield-models to estimate early-life reliability

Adit D. Singh, Victor P. Nelson, Thomas S. Barnett, 2003, IEEE Trans. Reliab..

Cell Aware and stuck-open tests

Adit D. Singh, 2016, 2016 21th IEEE European Test Symposium (ETS).

The effect of defect clustering on test transparency and defect levels

Adit D. Singh, C. Mani Krishna, 1993, Digest of Papers Eleventh Annual 1993 IEEE VLSI Test Symposium.

Reliability evaluation for integrated circuit with defective interconnect under electromigration

Abhijit Chatterjee, Adit D. Singh, Xiangdong Xuan, 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

Burn-in failures and local region yield: an integrated field-reliability model

Adit D. Singh, Victor P. Nelson, Thomas S. Barnett, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

Post-Manufacture Tuning for Nano-CMOS Yield Recovery Using Reconfigurable Logic

Abhijit Chatterjee, Adit D. Singh, Maryam Ashouei, 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A dual-Vt layout approach for statistical leakage variability minimization in nanometer CMOS

Abhijit Chatterjee, Adit D. Singh, Vivek De, 2005, 2005 International Conference on Computer Design.

An efficient channel routing algorithm for defective arrays

Hee Yong Youn, Adit D. Singh, 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

Achieving high transition delay fault coverage with partial DTSFF scan chains

Adit D. Singh, Gefu Xu, 2007, 2007 IEEE International Test Conference.

A Modular Fault-Tolerant Binary Tree Architecture with Short Links

Hee Yong Youn, Adit D. Singh, 1991, IEEE Trans. Computers.

A Secure Low-Cost Edge Device Authentication Scheme for the Internet of Things

Ujjwal Guin, Anthony Skjellum, Adit D. Singh, 2018, 2018 31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID).

Incorporating IDDQ Testing with BIST for Improved Coverage: An Experimental Study

Adit D. Singh, Walter W. Weber, 1997, J. Electron. Test..

Exploiting path delay test generation to develop better TDF tests for small delay defects

Adit D. Singh, Kewal K. Saluja, Virendra Singh, 2017, 2017 IEEE International Test Conference (ITC).

Detection of gate-oxide defects with timing tests at reduced power supply

Adit D. Singh, Chao Han, Xi Qian, 2012, 2012 IEEE 30th VLSI Test Symposium (VTS).

Yield and reliability prediction for DSM circuits

Adit D. Singh, Thomas S. Barnett, 2006 .

A self-timed structural test methodology for timing anomalies due to defects and process variations

Adit D. Singh, 2005, IEEE International Conference on Test, 2005..

Testing cross wire opens within complex gates

Adit D. Singh, Chao Han, 2015, 2015 IEEE 33rd VLSI Test Symposium (VTS).

Design of adaptive nanometer digital systems for effective control of soft error tolerance

Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril, 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

Special session 4B: Elevator talks

Michail Maniatakos, Masahiro Fujita, Adit D. Singh, 2013, VTS.

Relating yield models to burn-in fall-out in time

Adit D. Singh, Thomas S. Barnett, A. Singh, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Fast test application technique without fast scan clocks

Adit D. Singh, Gefu Xu, B. Vinnakota, 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

Diagnosing Multiple Slow Gates for Performance Tuning in the Face of Extreme Process Variations

Abhijit Chatterjee, Adit D. Singh, Xi Qian, 2011, 2011 Asian Test Symposium.

Scan Based Testing of Dual/Multi Core Processors for Small Delay Defects

Adit D. Singh, 2008, 2008 IEEE International Test Conference.

Exploiting power supply ramp rate for calibrating cell strength in SRAM PUFs

Abhijit Chatterjee, Ujjwal Guin, Adit D. Singh, 2018, 2018 IEEE 19th Latin-American Test Symposium (LATS).

Estimating burn-in fall-out for redundant memory

Adit D. Singh, Victor P. Nelson, Thomas S. Barnett, 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

Output Hazard-Free Transition Delay Fault Test Generation

Vishwani D. Agrawal, Adit D. Singh, Sreekumar Menon, 2009, VTS.

Experiments in detecting delay faults using multiple higher frequency clocks and results from neighboring die

Haihua Yan, Adit D. Singh, 2003, International Test Conference, 2003. Proceedings. ITC 2003..

Adaptive voting for fault (VFF) node scheme for distributed self-diagnosis

Hee Yong Youn, Adit D. Singh, Jae Young Lee, 1993, FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing.

Best paper

Bernd Becker, Adit D. Singh, 2017, ETS.

Four-valued interface circuits for NMOS VLSI

Adit D. Singh, 1987 .

Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril, 2005, IEEE Trans. Very Large Scale Integr. Syst..

Challenge Engineering and Design of Analog Push Pull Amplifier Based Physically Unclonable Function for Hardware Security

Abhijit Chatterjee, Adit D. Singh, Sabyasachi Deyati, 2015, 2015 IEEE 24th Asian Test Symposium (ATS).

Low-Power Dual Vth Pseudo Dual Vdd Domino Circuits

Abhijit Chatterjee, Adit D. Singh, Yuvraj Singh, 2004 .

Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?

Abhijit Chatterjee, Jacob A. Abraham, Christos A. Papachristou, 2009, 2009 15th IEEE International On-Line Testing Symposium.

Yield-reliability modeling for fault tolerant integrated circuits

Adit D. Singh, Victor P. Nelson, Thomas S. Barnett, 2001, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors

Abhijit Chatterjee, Miodrag Potkonjak, Adit D. Singh, 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

Redundancy implications for early-life reliability: experimental verification of an integrated yield-reliability model

Adit D. Singh, Matt Grady, Kathleen G. Purdy, 2002, Proceedings. International Test Conference.

Low voltage test in place of fast clock in DDSI delay test

Haihua Yan, Adit D. Singh, Gefu Xu, 2005, Sixth international symposium on quality electronic design (isqed'05).

Yield-reliability modeling: experimental verification and application to burn-in reduction

Adit D. Singh, Matt Grady, Kathleen G. Purdy, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

On Area Efficient and Fault Tolerant Tree Embedding In VLSI

Hee Yong Youn, Adit D. Singh, 1987, ICPP.

Path Delay Tuning for Performance Gain in the Face of Random Manufacturing Variations

Adit D. Singh, Ahmed Faraz, Kautalya Mishra, 2011, 2011 24th Internatioal Conference on VLSI Design.

Scan cell design for launch-on-shift delay tests with slow scan enable

Adit D. Singh, Gefu Xu, A. Singh, 2007, IET Comput. Digit. Tech..

An IDDQ sensor for concurrent timing error detection

Adit D. Singh, Christopher G. Knight, Victor P. Nelson, 1997, 1997 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

Multimode scan: Test per clock BIST for IP cores

Adit D. Singh, Michael Gössel, Egor S. Sogomonyan, 2003, TODE.

A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing

Adit D. Singh, Michael Gössel, Egor S. Sogomonyan, 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

Low-power dual V/sub th/ pseudo dual V/sub dd/ domino circuits

Adit D. Singh, Abhijit Chatterjee, Abdulkadir Utku Diril, 2004 .

Low-power dual V/sub th/ pseudo dual V/sub dd/ domino circuits

Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril, 2004, Proceedings. SBCCI 2004. 17th Symposium on Integrated Circuits and Systems Design (IEEE Cat. No.04TH8784).

Test application time minimization for RAS using basis optimization of column decoder

Adit D. Singh, Kewal K. Saluja, Virendra Singh, 2010, Proceedings of 2010 IEEE International Symposium on Circuits and Systems.

Error detection and recovery in better-than-worst-case timing designs

Adit D. Singh, 2014, 2014 19th IEEE European Test Symposium (ETS).

Exploiting defect clustering to screen bare die for infant mortality failures: an experimental study

Adit D. Singh, David R. Lakin, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

An Efficient Transition Detector Exploiting Charge Sharing

Adit D. Singh, Yu Wang, 2015, 2015 28th International Conference on VLSI Design.

A High Throughput Multiplier Design Exploiting Input Based Statistical Distribution in Completion Delays

Abhijit Chatterjee, Adit D. Singh, Ravi Tej Uppu, 2013, 2013 26th International Conference on VLSI Design and 2013 12th International Conference on Embedded Systems.

Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths

Adit D. Singh, Ilia Polian, Ravi Tej Uppu, 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

Incorporating IDDQ testing in BIST: improved coverage through test diversity

Adit D. Singh, Jason P. Hurst, 1994, Proceedings of IEEE VLSI Test Symposium.

Identifying high variability speed-limiting paths under aging

Adit D. Singh, Kewal K. Saluja, Virendra Singh, 2017, 2017 18th IEEE Latin American Test Symposium (LATS).

Output hazard-free transition tests for silicon calibrated scan based delay testing

Adit D. Singh, Gefu Xu, 2006, 24th IEEE VLSI Test Symposium.

A Near Optimal Adaptive Row Modular Design for Efficiently Reconfiguring the Processor Array in VLSI

Hee Yong Youn, Adit D. Singh, 1989, ICPP.

Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for Large Area VLSI Processor Arrays

Adit D. Singh, 1988, IEEE Trans. Computers.

High Resolution Pulse Propagation Driven Trojan Detection in Digital Logic: Optimization Algorithms and Infrastructure

Abhijit Chatterjee, Adit D. Singh, Sabyasachi Deyati, 2014, 2014 IEEE 23rd Asian Test Symposium.

Modified T-Flip-Flop based scan cell for RAS

Adit D. Singh, Kewal K. Saluja, Virendra Singh, 2010, 2010 15th IEEE European Test Symposium.

Fault tolerance in VLSI circuits

Israel Koren, Adit D. Singh, 1990, Computer.

A novel design-for-security (DFS) architecture to prevent unauthorized IC overproduction

Ujjwal Guin, Adit D. Singh, Ziqi Zhou, 2017, 2017 IEEE 35th VLSI Test Symposium (VTS).

Chip test optimization using defect clustering information

Adit D. Singh, C. Mani Krishna, 1992, [1992] Digest of Papers. FTCS-22: The Twenty-Second International Symposium on Fault-Tolerant Computing.

Adapting to adaptive testing

Kenneth M. Butler, Erik Jan Marinissen, Adit D. Singh, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

SEU Tolerant Robust Latch Design

Masahiro Fujita, Adit D. Singh, Virendra Singh, 2012, VDAT.

On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits

Sudhakar M. Reddy, Bernd Becker, Adit D. Singh, 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Scan Delay Testing of Nanometer SoCs

Adit D. Singh, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Early error detection in systems-on-chip for fault-tolerance and at-speed debugging

Adit D. Singh, Michael Gössel, Egor S. Sogomonyan, 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

SSTKR: Secure and Testable Scan Design through Test Key Randomization

Adit D. Singh, Virendra Singh, Mohammed Abdul Razzaq, 2011, 2011 Asian Test Symposium.

Testability evaluation of sequential designs incorporating the multi-mode scannable memory element

Adit D. Singh, Michael Gössel, Egor S. Sogomonyan, 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS

Abhijit Chatterjee, Adit D. Singh, Maryam Ashouei, 2008, 21st International Conference on VLSI Design (VLSID 2008).

Scan-path with directly duplicated and inverted duplicated registers

Adit D. Singh, Michael Gössel, Egor S. Sogomonyan, 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

On Implementing Large Binary Tree Architectures in VLSI and WSI

Hee Yong Youn, Adit D. Singh, 1989, IEEE Trans. Computers.

Scan based two-pattern tests: should they target opens instead of TDFs?

Adit D. Singh, 2015, 2015 16th Latin-American Test Symposium (LATS).

On Optimizing Wafer-Probe Testing for Product Quality Using Die-Yield Prediction

Adit D. Singh, C. Mani Krishna, 1991, 1991, Proceedings. International Test Conference.

Detecting Recycled SoCs by Exploiting Aging Induced Biases in Memory Cells

Ujjwal Guin, Adit D. Singh, Wendong Wang, 2019, 2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

Two-Pattern ∆IDDQ Test for Recycled IC Detection

Vishwani D. Agrawal, Ujjwal Guin, Adit D. Singh, 2019, 2019 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID).

Capture Power Reduction for Modular System-on-Chip Test

Erik G. Larsson, Adit D. Singh, Jaynarayan T. Tudu, 2009 .

A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS

Adit D. Singh, 2009, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

A differential built-in current sensor design for high speed IDDQ testing

Adit D. Singh, Jason P. Hurst, 1995, Proceedings of the 8th International Conference on VLSI Design.

Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing

Adit D. Singh, Virendra Singh, K. G. Deepak, 2009, 2009 Asian Test Symposium.

Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG

Sudhakar M. Reddy, Bernd Becker, Adit D. Singh, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Current Sensing Completion Detection for high speed and area efficient arithmetic

Adit D. Singh, Balapradeep Gadamsetti, 2010, 2010 IEEE Asia Pacific Conference on Circuits and Systems.

A delay test to differentiate resistive interconnect faults from weak transistor defects

Haihua Yan, Adit D. Singh, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing

Adit D. Singh, Michael Gössel, Egor S. Sogomonyan, 1999, J. Electron. Test..

Pseudo Dual Supply Voltage Domino Logic Design

Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril, 2005, J. Low Power Electron..

Device aging: A reliability and security concern

Abhijit Chatterjee, Francky Catthoor, Adit D. Singh, 2018, 2018 IEEE 23rd European Test Symposium (ETS).

Timing Variation Adaptive Pipeline Design: Using Probabilistic Activity Completion Sensing with Backup Error Resilience

Abhijit Chatterjee, Adit D. Singh, Debesh Bhatta, 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

On the testing of hazard activated open defects

Adit D. Singh, Chao Han, 2014, 2014 International Test Conference.

Sizing CMOS circuits for increased transient error tolerance

Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril, 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

Efficient SAT-based generation of hazard-activated TSOF tests

Sudhakar M. Reddy, Bernd Becker, Adit D. Singh, 2017, 2017 IEEE 35th VLSI Test Symposium (VTS).

New JETTA Editors, 2006

Adit D. Singh, Bashir M. Al-Hashimi, Dimitris Gizopoulos, 2006, J. Electron. Test..

Adaptive Test Methods for High IC Quality and Reliability

Adit D. Singh, 2016, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID).

T2: Statistical Methods for VLSI Test and Burn-in Optimization

Adit D. Singh, 2005, 14th Asian Test Symposium (ATS'05).

Tutorials [2 abstracts]

Krishnendu Chakrabarty, Adit D. Singh, 2013, ATS 2013.

Delay Defect Characterization Using Low Voltage Test

Adit D. Singh, Gefu Xu, Haihua Yan, 2005, 14th Asian Test Symposium (ATS'05).

Hazard Initialized LOC Tests for TDF Undetectable CMOS Open Defects

Adit D. Singh, Chao Han, 2013, 2013 22nd Asian Test Symposium.

ADTS: an array defect-tolerance scheme for wafer scale gate arrays

Adit D. Singh, 1995, Proceedings of International Workshop on Defect and Fault Tolerance in VLSI.

Analysis of the die test optimization algorithm for negative binomial yield statistics

Adit D. Singh, C. Mani Krishna, 1992, Digest of Papers. 1992 IEEE VLSI Test Symposium.

Adit D. Singh, C. Mani Krishna, 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.