K. Bernstein

Turning silicon on its edge [double gate CMOS/FinFET technology]

E.J. Nowak, I. Aller, T. Ludwig, 2004, IEEE Circuits and Devices Magazine.

Variability and power management in sub-100nm SOI technology for reliable high performance systems

K. Bernstein, Shih-Hsien Lo, K. Das, 2008, 2008 IEEE International SOI Conference.

Scaling, power, and the future of CMOS

K. Bernstein, Elad Alon, Mark Horowitz, 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

Challenges for post-CMOS devices & architectures

K. Bernstein, J. Welser, 2011, 69th Device Research Conference.

Alternative transistor concepts

K. Bernstein, Max Planck, Heike Riel, 2011, 69th Device Research Conference.

CMOS circuit technology for sub-ambient temperature operation

I. Aller, K. Bernstein, H. Schettler, 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

Technology Circuit Co-Design for High Performance Logic

K. Bernstein, N.J. Rohrer, 2007, 2007 IEEE International Electron Devices Meeting.

Soft error rate scaling for emerging SOI technology options

K. Bernstein, H.-S.P. Wong, P. Oldiges, 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

On the integration of CMOS with hybrid crystal orientations

K. Bernstein, P. Oldiges, M. Ieong, 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

Effects of Gate-to-Body Tunneling Current on PD/SOI CMOS Circuits

Ching-Te Chuang, K. Bernstein, R. Puri, 2001 .