Seiya Tanikawa

Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC

Mitsumasa Koyanagi, Tetsu Tanaka, Takafumi Fukushima, 2015, 2015 International 3D Systems Integration Conference (3DIC).

Novel local stress evaluation method in 3D IC using DRAM cell array with planar mOS capacitors

Mitsumasa Koyanagi, Tetsu Tanaka, Takafumi Fukushima, 2015, 2015 International 3D Systems Integration Conference (3DIC).

Degradation of Memory Retention Characteristics in DRAM Chip by Si Thinning for 3-D Integration

Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka, 2013, IEEE Electron Device Letters.

Impacts of 3-D Integration Processes on Memory Retention Characteristics in Thinned DRAM Chip for High-Reliable 3-D DRAM

Mitsumasa Koyanagi, Takafumi Fukushima, Mariappan Murugesan, 2014, IEEE Transactions on Electron Devices.

Impacts of Cu contamination in 3D integration process on memory retention characteristics in thinned DRAM chip

Mitsumasa Koyanagi, Takafumi Fukushima, Tetsu Tanaka, 2014, 2014 IEEE International Reliability Physics Symposium.