Themistoklis Haniotakis

发表

A Current Mode, Parallel, Two-Rail Code Checker

Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, 2008, IEEE Transactions on Computers.

The use of pre-evaluation phase in dynamic CMOS logic

Yiorgos Tsiatouhas, Themistoklis Haniotakis, A. Rao, 2005, IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design (ISVLSI'05).

A 1Kx32 bit WDSRAM page with rapid write access

Themistoklis Haniotakis, Theodoros Simopoulos, George Alexiou, 2018, 2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS).

Power-delay-area efficient design of vedic multiplier using adaptable manchester carry chain adder

Themistoklis Haniotakis, Raghava Katreepalli, T. Haniotakis, 2017, 2017 International Conference on Communication and Signal Processing (ICCSP).

A Data Capturing Method for Buses on Chip

Spyros Tragoudas, Themistoklis Haniotakis, Kedar Karmarkar, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

An efficient comparative concurrent Built-In Self-Test technique

Themistoklis Haniotakis, Constantin Halatsis, Ioannis Voyiatzis, 1995, Proceedings of the Fourth Asian Test Symposium.

Energy-efficient synchronous counter design with minimum hardware overhead

Themistoklis Haniotakis, Raghava Katreepalli, 2017, 2017 International Conference on Communication and Signal Processing (ICCSP).

A new method to identify threshold logic functions

Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Glitch Control with Dynamic Receiver Threshold Adjustment

Haibo Wang, Spyros Tragoudas, Themistoklis Haniotakis, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Identification of delay defects on embedded paths using one current sensor

Spyros Tragoudas, Themistoklis Haniotakis, Wisam Aljubouri, 2016, 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS).

A Design Technique for Energy Reduction in NORA CMOS Logic

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

Memory write speed up via multi voltage driver on CeidMem Library

Themistoklis Haniotakis, Theodoros Simopoulos, G. Ph. Alexiou, 2016 .

A High-Performance Bus Architecture for Strongly Coupled Interconnects

Spyros Tragoudas, Themistoklis Haniotakis, M. N. Skoufis, 2008, ISQED 2008.

Design and evaluation of a security scheme for sensor networks

Spyros Tragoudas, Themistoklis Haniotakis, Khadija Stewart, 2005, Sixth international symposium on quality electronic design (isqed'05).

A class of easily path delay fault testable circuits

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Haridimos T. Vergos, 2000, 2000 Southwest Symposium on Mixed-Signal Design (Cat. No.00EX390).

A Built In Test circuit for waveform classification at high frequencies

Themistoklis Haniotakis, Konstantinos Poulos, 2020, 2020 IEEE 29th North Atlantic Test Workshop (NATW).

A Design Technique for Energy Reduction in

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, 2006 .

A new scheme for effective I/sub DDQ/ testing in deep submicron

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, 2000, Proceedings 2000 IEEE International Workshop on Defect Based Testing (Cat. No.PR00637).

Extending the viability of I/sub DDQ/ testing in the deep submicron era

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, 2002, Proceedings International Symposium on Quality Electronic Design.

High performance and low power dynamic circuit design

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Zaher Owda, 2011, 2011 IEEE 9th International New Circuits and systems conference.

An enhanced approach to reduce test application time through limited shift operations in scan chains

Themistoklis Haniotakis, Konstantinos Poulos, Jayasurya Kuchi, 2017, 2017 IEEE North Atlantic Test Workshop (NATW).

A Methodology for Transistor-Efficient Supergate Design

Themistoklis Haniotakis, Dimitrios Kagaris, D. Kagaris, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

CeidMem: A compact Static Memory Library

Themistoklis Haniotakis, Theodoros Simopoulos, G. Ph. Alexiou, 2016 .

Delay Analysis for an N-Input Current Mode Threshold Logic Gate

Spyros Tragoudas, Themistoklis Haniotakis, Chandra Babu Dara, 2012, 2012 IEEE Computer Society Annual Symposium on VLSI.

Fast, parallel two-rail code checker with enhanced testability

Aristides Efthymiou, Sotirios Matakias, Yiorgos Tsiatouhas, 2005, 11th IEEE International On-Line Testing Symposium.

ARIAN: A Scalable Method for Adding aRbItrAry Numbers on Modern Processors

Iraklis Anagnostopoulos, Themistoklis Haniotakis, Konstantinos Poulos, 2020, ISCAS.

An improved method for identifying linear dependencies in path delay faults

Spyros Tragoudas, Edward Flanigan, Themistoklis Haniotakis, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

High Speed Power Efficient Carry Select Adder Design

Themistoklis Haniotakis, Raghava Katreepalli, 2017, 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

Ultra fast and low cost parallel two-rail code checker targeting high fan-in applications

Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, 2004, IEEE Computer Society Annual Symposium on VLSI.

A power-delay efficient carry select adder

Themistoklis Haniotakis, Raghava Katreepalli, Drona Meruguboina, 2017, 2017 2nd International Conference for Convergence in Technology (I2CT).

A new dynamic circuit design technique for high performance TSC checker implementations [totally sel

Themistoklis Haniotakis, Y. Tsiatouhas, A. Rao, 2004 .

Low power and high speed current-mode memristor-based TLGs

Spyros Tragoudas, Themistoklis Haniotakis, Chandra Babu Dara, 2013, 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS).

Fast march tests for defects in resistive memory

Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis, 2015, Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH´15).

Implementation Guidelines of WDSRAM and Comparison with Typical SRAM Using Nanoscale Hierarchical Implementation Model

Themistoklis Haniotakis, Theodoros Simopoulos, George Ph. Alexiou, 2019, J. Circuits Syst. Comput..

Concurrent detection of soft errors based on current monitoring

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Costas Efstathiou, 2001, Proceedings Seventh International On-Line Testing Workshop.

Testable Designs of Multiple Precharged Domino Circuits

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Costas Efstathiou, 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Securing sensor networks: A novel approach that combines encoding, uncorrelation and node disjoint transmission

Spyros Tragoudas, Themistoklis Haniotakis, Khadija Stewart, 2012, Ad Hoc Networks.

A hierarchical architecture for concurrent soft error detection based on current sensing

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, 2002, Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002).

Path delay fault testing of ICs with embedded intellectual property blocks

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Haridimos T. Vergos, 1999, DATE '99.

A zero aliasing built-in self test technique for delay fault testing

Yiorgos Tsiatouhas, Themistoklis Haniotakis, 1999, Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (EFT'99).

A High-Performance Bus Architecture for Strongly Coupled Interconnects

Spyros Tragoudas, Themistoklis Haniotakis, Kedar Karmarkar, 2008, 9th International Symposium on Quality Electronic Design (isqed 2008).

Diagnosis of segment delay defects with current sensing

Spyros Tragoudas, Themistoklis Haniotakis, Wisam Aljubouri, 2014, 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

A new dynamic circuit design technique for high performance TSC checker implementations [totally self checking circuits]

Yiorgos Tsiatouhas, Themistoklis Haniotakis, A. Rao, 2004, Proceedings. 10th IEEE International On-Line Testing Symposium.

A current monitoring technique for IDDQ testing in digital integrated circuits

Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, 2015, Integr..

C-testable one-dimensional ILAs with respect to path delay faults: theory and applications

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Dimitris Nikolos, 1998, Proceedings 1998 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (Cat. No.98EX223).

On path delay fault testing of multiplexer-based shifters

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Michael Nicolaidis, 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

Delay Analysis for Current Mode Threshold Logic Gate Designs

Spyros Tragoudas, Themistoklis Haniotakis, Chandra Babu Dara, 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

More Efficient Testing of Metal-Oxide Memristor–Based Memory

Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis, 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Implementation of a 256x8 Sector Size SRAM grid with memory write speedup on CeidMem library

Themistoklis Haniotakis, Theodoros Simopoulos, George Ph Alexiou, 2016, 2016 5th International Conference on Modern Circuits and Systems Technologies (MOCAST).

A versatile built-in self test scheme for delay fault testing (poster paper)

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, 2000, DATE '00.

An embedded IDDQ testing circuit and technique

Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, 2005, 2005 12th IEEE International Conference on Electronics, Circuits and Systems.

ATPG for transition faults of pipelined threshold logic circuits

Spyros Tragoudas, Themistoklis Haniotakis, Ashok Kumar Palaniswamy, 2014, 2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Power efficient synchronous counter design

Themistoklis Haniotakis, Raghava Katreepalli, T. Haniotakis, 2019, Comput. Electr. Eng..

A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs

Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, 2004, J. Electron. Test..

A sense amplifier based circuit for concurrent detection of soft and timing errors in CMOS ICs

Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

Efficient Totally Self-Checking Checkers for a Class of Borden Codes

Themistoklis Haniotakis, Antonis M. Paschalis, Dimitris Nikolos, 1995, IEEE Trans. Computers.

A Generalized Approach to Implement Efficient CMOS-Based Threshold Logic Functions

Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis, 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

A Metric for Weight Assignment to Optimize the Performance of MOBILE Threshold Logic Gate

Spyros Tragoudas, Themistoklis Haniotakis, Chandra Babu Dara, 2011, 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.

ATPG for Delay Defects in Current Mode Threshold Logic Circuits

Spyros Tragoudas, Themistoklis Haniotakis, Ashok Kumar Palaniswamy, 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Transistor-Level Synthesis for Low-Power Applications

Themistoklis Haniotakis, Dimitrios Kagaris, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

New test pattern generation units for NPSF oriented memory built-in self test

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

Security enhancement through multiple path transmission in ad hoc networks

Spyros Tragoudas, Themistoklis Haniotakis, Constantinos Kalapodas, 2004, 2004 IEEE International Conference on Communications (IEEE Cat. No.04CH37577).

Reduced test application time based on reachability analysis

Spyros Tragoudas, Themistoklis Haniotakis, G. Pani, 2005, Sixth international symposium on quality electronic design (isqed'05).

SRAM oriented memory sense amplifier design in 0.18 /spl mu/m CMOS technology

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

On testability of multiple precharged domino logic

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Dimitris Nikolos, 2000, Proceedings IEEE 2000 First International Symposium on Quality Electronic Design (Cat. No. PR00525).

A security protocol for sensor networks

Spyros Tragoudas, Themistoklis Haniotakis, Khadija Stewart, 2005, GLOBECOM '05. IEEE Global Telecommunications Conference, 2005..

A unified framework for generating all propagation functions for logic errors and events

Spyros Tragoudas, Themistoklis Haniotakis, Maria K. Michael, 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Memory-Less Pipeline Dynamic Circuit Design Technique

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Zaher Owda, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

A compact built-in current sensor for I/sub DDQ/ testing

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Dimitris Nikolos, 2000, Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646).

Transistor-level optimization of supergates

Themistoklis Haniotakis, Dimitrios Kagaris, D. Kagaris, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Low-Power and High Performance Sinusoidal Clocked Dynamic Circuit Design

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Raghava Katreepalli, 2016, 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI).

An embedded I/sub DDQ/ testing architecture and technique

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

Reducing power, area, and delay of threshold logic gates considering non-integer weights

Seyed Nima Mozaffari, Spyros Tragoudas, Themistoklis Haniotakis, 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).