Angela Arapoyanni

发表

A Current Mode, Parallel, Two-Rail Code Checker

Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, 2008, IEEE Transactions on Computers.

An Embedded Test Circuit for RF Single Ended Low Noise Amplifiers

Yiorgos Tsiatouhas, Angela Arapoyanni, Lampros Dermentzoglou, 2007, 2007 14th IEEE International Conference on Electronics, Circuits and Systems.

A Built-In Voltage Measurement Technique for the Calibration of RF Mixers

Yiorgos Tsiatouhas, Angela Arapoyanni, John Liaperdos, 2013, IEEE Transactions on Instrumentation and Measurement.

Cost and power efficient timing error tolerance in flip-flop based microprocessor cores

Yiorgos Tsiatouhas, Angela Arapoyanni, Stefanos Valadimas, 2012, 2012 17th IEEE European Test Symposium (ETS).

A Build-In Self-Test technique for RF Mixers

Yiorgos Tsiatouhas, Angela Arapoyanni, Lampros Dermentzoglou, 2010, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.

A Design for Testability Scheme for CMOS LC-Tank Voltage Controlled Oscillators

Yiorgos Tsiatouhas, Angela Arapoyanni, Lampros Dermentzoglou, 2004, J. Electron. Test..

High performance level restoration circuits for low-power reduced-swing interconnect schemes

Angela Arapoyanni, Y. Moisiadis, I. Bouras, 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).

A Design Technique for Energy Reduction in NORA CMOS Logic

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.

High performance level restoration circuits

Angela Arapoyanni, I. Bouras, Yiannis Moisiadis, 2001 .

A CMOS charge pump for low voltage operation

Angela Arapoyanni, Yiannis Moisiadis, Ilias Bouras, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

A Built-In-Test Circuit for RF Differential Low Noise Amplifiers

Yiorgos Tsiatouhas, Angela Arapoyanni, Lampros Dermentzoglou, 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

Charge Pump Circuits for Low-voltage Applications

Angela Arapoyanni, Yiannis Moisiadis, Ilias Bouras, 2002, VLSI Design.

A Design Technique for Energy Reduction in

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, 2006 .

A new scheme for effective I/sub DDQ/ testing in deep submicron

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, 2000, Proceedings 2000 IEEE International Workshop on Defect Based Testing (Cat. No.PR00637).

Novel domino logic designs

Yiorgos Tsiatouhas, Angela Arapoyanni, Th. Haniotakis, 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

Extending the viability of I/sub DDQ/ testing in the deep submicron era

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, 2002, Proceedings International Symposium on Quality Electronic Design.

The Time Dilation Technique for Timing Error Tolerance

Yiorgos Tsiatouhas, Angela Arapoyanni, Andreas Floros, 2014, IEEE Transactions on Computers.

A versatile built-in self test scheme for delay fault testing

Yiorgos Tsiatouhas, Angela Arapoyanni, Dimitris Nikolos, 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

A static differential double edge-triggered flip-flop based on clock racing

Angela Arapoyanni, I. Bouras, Yiannis Moisiadis, 2001 .

A design for testability technique for mixed-signal differential circuits

Yiorgos Tsiatouhas, Angela Arapoyanni, L. Dermentzoglou, 2005 .

Timing error tolerance in nanometer ICs

Yiorgos Tsiatouhas, Angela Arapoyanni, Stefanos Valadimas, 2010, 2010 IEEE 16th International On-Line Testing Symposium.

Fast, parallel two-rail code checker with enhanced testability

Aristides Efthymiou, Sotirios Matakias, Yiorgos Tsiatouhas, 2005, 11th IEEE International On-Line Testing Symposium.

NBTI aging tolerance in pipeline based designs NBTI

Yiorgos Tsiatouhas, Angela Arapoyanni, Katerina Katsarou, 2013, 2013 IEEE 19th International On-Line Testing Symposium (IOLTS).

A high-performance low-power static differential double edge-triggered flip-flop

Angela Arapoyanni, Lampros Dermentzoglou, Yiannis Moisiadis, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

Timing error mitigation in microprocessor cores

Yiorgos Tsiatouhas, Angela Arapoyanni, Stefanos Valadimas, 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Ultra fast and low cost parallel two-rail code checker targeting high fan-in applications

Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, 2004, IEEE Computer Society Annual Symposium on VLSI.

A 0.35 /spl mu/m SiGe BiCMOS front end for GSM low IF cellular receiver applications

Angela Arapoyanni, G. Kamoulakos, L. Dermentzoglou, 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

Analog-to-Digital Interface for Heterodyne Receivers

Angela Arapoyanni, Lampros Dermentzoglou, Aristodemos Pnevmatikakis, 2002, J. Circuits Syst. Comput..

Device simulation of a n-DMOS cell with trench isolation

Yiorgos Tsiatouhas, Angela Arapoyanni, G. Kamoulakos, 2001 .

On the reuse of existing error tolerance circuitry for low power scan testing

Yiorgos Tsiatouhas, Angela Arapoyanni, Anthi Anastasiou, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

A hierarchical architecture for concurrent soft error detection based on current sensing

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, 2002, Proceedings of the Eighth IEEE International On-Line Testing Workshop (IOLTW 2002).

Effective Timing Error Tolerance in Flip-Flop Based Core Designs

Yiorgos Tsiatouhas, Angela Arapoyanni, Stefanos Valadimas, 2013, J. Electron. Test..

A Pipeline Architecture Incorporating a Low-Cost Error Detection and Correction Mechanism

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

Timing Error Tolerance in Small Core Designs for SoC Applications

Yiorgos Tsiatouhas, Angela Arapoyanni, Stefanos Valadimas, 2016, IEEE Transactions on Computers.

A current monitoring technique for IDDQ testing in digital integrated circuits

Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, 2015, Integr..

Dynamic back bias CMOS driver for low-voltage applications

Angela Arapoyanni, Y. Moisiadis, I. Bouras, 2000 .

A direct conversion receiver analysis for multistandard wireless applications

Angela Arapoyanni, L. Dermentzoglou, A. Pneumatikakis, 2000, 2000 10th Mediterranean Electrotechnical Conference. Information Technology and Electrotechnology for the Mediterranean Countries. Proceedings. MeleCon 2000 (Cat. No.00CH37099).

A novel scheme for testing radio frequency voltage controlled oscillators

Yiorgos Tsiatouhas, Angela Arapoyanni, Lampros Dermentzoglou, 2003, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003.

Adjustable RF Mixers' Alternate Test Efficiency Optimization by the Reduction of Test Observables

Yiorgos Tsiatouhas, Angela Arapoyanni, John Liaperdos, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A 900 MHz/1800 MHz/1900 MHz superhet receiver engaging high IF1 for image rejection

Angela Arapoyanni, L. Dermentzoglou, A. Pneumatikakis, 2000, Proceedings of the 2000 Third IEEE International Caracas Conference on Devices, Circuits and Systems (Cat. No.00TH8474).

Timing Error Tolerance in Pipeline Based Core Designs

Angela Arapoyanni, Stefanos Valadimas, 2014, Panhellenic Conference on Informatics.

Fast deployment of alternate analog test using Bayesian model fusion

Xin Li, Yiorgos Tsiatouhas, Angela Arapoyanni, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A high speed low power CMOS clock driver using charge recycling technique

Angela Arapoyanni, Ilias Bouras, Yiannis Liaperdos, 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

Scan chain based at-speed diagnosis in the presence of scan output compaction schemes

Yiorgos Tsiatouhas, Angela Arapoyanni, Helen-Maria Dounavi, 2015, Panhellenic Conference on Informatics.

Management of charge pump circuits

Yiorgos Tsiatouhas, Angela Arapoyanni, George Kamoulakos, 2000, Integr..

A versatile built-in self test scheme for delay fault testing (poster paper)

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, 2000, DATE '00.

An embedded IDDQ testing circuit and technique

Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, 2005, 2005 12th IEEE International Conference on Electronics, Circuits and Systems.

A multimode extra high IF1 image rejection receiver for TDMA applications

Angela Arapoyanni, Lampros Dermentzoglou, Aristodemos Pnevmatikakis, 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).

A test pattern generation unit for memory NPSF built-in self test

Yiorgos Tsiatouhas, Angela Arapoyanni, George Kamoulakos, 2000, ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445).

A built-in self-test scheme for differential ring oscillators

Yiorgos Tsiatouhas, Angela Arapoyanni, Lampros Dermentzoglou, 2005, Sixth international symposium on quality electronic design (isqed'05).

A method for the estimation of defect detection probability of analog/RF defect-oriented tests

Yiorgos Tsiatouhas, Angela Arapoyanni, John Liaperdos, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

A test and calibration strategy for adjustable RF circuits

Yiorgos Tsiatouhas, Angela Arapoyanni, John Liaperdos, 2013 .

A Circuit for Concurrent Detection of Soft and Timing Errors in Digital CMOS ICs

Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, 2004, J. Electron. Test..

Testing wireless transceivers' RF front-ends utilizing defect-oriented BIST techniques

Yiorgos Tsiatouhas, Angela Arapoyanni, Lampros Dermentzoglou, 2012, 2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012).

Reliability and defectivity comparison of n- and p-channel SLS ELA polysilicon TFTs fabricated with a novel crystallization technique

Angela Arapoyanni, George J. Papaioannou, Dimitrios N. Kouvatsos, 2008, Microelectron. Reliab..

Building blocks for a 100 MS/s, 10-b, 1.8 V CMOS cascaded folding & interpolating A/D converter

Angela Arapoyanni, Stamatis Bouras, Christos Kokozidis, 2003, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003.

A sense amplifier based circuit for concurrent detection of soft and timing errors in CMOS ICs

Sotirios Matakias, Yiorgos Tsiatouhas, Themistoklis Haniotakis, 2003, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003..

Single event upset tolerance in flip-flop based microprocessor cores

Adrian Evans, Yiorgos Tsiatouhas, Angela Arapoyanni, 2012, 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

New test pattern generation units for NPSF oriented memory built-in self test

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

An extra low noise 1.8 GHz voltage controlled oscillator in 0.35 SiGe BiCMOS technology

Angela Arapoyanni, G. Kamoulakos, L. Dermentzoglou, 2002, 9th International Conference on Electronics, Circuits and Systems.

Machine Learning in Alternate Testing of Integrated Circuits

Yiorgos Tsiatouhas, Angela Arapoyanni, John Liaperdos, 2019, Learning and Analytics in Intelligent Systems.

A new technique for IDDQ testing in nanometer technologies

Yiorgos Tsiatouhas, Angela Arapoyanni, Dimitris Nikolos, 2002, Integr..

On the latency, energy and area of checkpointed, superscalar register alias tables

Angela Arapoyanni, Andreas G. Veneris, Andreas Moshovos, 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

A new flash memory sense amplifier in 0.18 /spl mu/m CMOS technology

Yiorgos Tsiatouhas, Angela Arapoyanni, A. Chrisanthopoulos, 2001, ICECS 2001. 8th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.01EX483).

State reduction for efficient digital calibration of analog/RF integrated circuits

Yiorgos Tsiatouhas, Angela Arapoyanni, John Liaperdos, 2017 .

SRAM oriented memory sense amplifier design in 0.18 /spl mu/m CMOS technology

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

High fan-in differential current mirror logic

Yiorgos Tsiatouhas, Angela Arapoyanni, 2006, 2006 IEEE International Symposium on Circuits and Systems.

A Scan Flip-Flop for Low-Power Scan Operation

Yiorgos Tsiatouhas, Angela Arapoyanni, Dionisis Skias, 2007, 2007 14th IEEE International Conference on Electronics, Circuits and Systems.

An embedded I/sub DDQ/ testing architecture and technique

Yiorgos Tsiatouhas, Themistoklis Haniotakis, Angela Arapoyanni, 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..