Kuroda Yasuto

发表

A 250Msps, 0.5W eDRAM-based Search Engine applying full-route capacity dedicated FIB application

Yamamoto Koji, Kuroda Yasuto, Yano Yuji, 2012 .

Performance Evaluation on Energy Consumption of Sliced Packet Buffer with Traffic Volume and Occupancy Adaptation

Ata Shingo, Oka Ikuo, Kuroda Yasuto, 2012 .

Super parallel SIMD processor with CAM based high-speed pattern matching capability

Kumaki Takeshi, Kuroda Yasuto, Arimoto Kazutami, 2006 .

Cost Evaluation and Parameter Optimization of the Fast Forwarding Engine using Standard Memory

Ata Shingo, Oka Ikuo, Yamamoto Koji, 2010 .

Hardware Implementation of Fast Forwarding Engine using Standard Memory and Dedicated Circuit

Ata Shingo, Oka Ikuo, Yamamoto Koji, 2010 .

Acceleration of Multimedia Data Processing with CAM-Enhanced Massive-Parallel SIMD Matrix Processor

Kumaki Takeshi, Kuroda Yasuto, Arimoto Kazutami, 2007 .

Latency Reduction in Energy-aware Routers Using Grained Traffic Prediction

Ata Shingo, Oka Ikuo, Kuroda Yasuto, 2012 .

Implementation and Evaluation of Energy-aware Search Hardware Applicable to Wide and Sparse Rules

Ata Shingo, Oka Ikuo, Kuroda Yasuto, 2015 .

Advanced memory controller for Low power router architecture

Murata Masayuki, Ata Shingo, Hasegawa Go, 2012 .

Multiple CAM Matches and Self-adapting Codeword Table for Optimized Real-time Huffman Encoding

Kumaki Takeshi, Kuroda Yasuto, Arimoto Kazutami, 2006 .

Parameters to Minimize an Energy Overhead of Two Dimensional Sliced Packet Buffer

Ata Shingo, Oka Ikuo, Kuroda Yasuto, 2013 .

Low-Power and High-Speed Search Engine by Multi-dimensional TCAM Architecture with Parallel Pipelined Subdivided Structure

Ata Shingo, Oka Ikuo, Kuroda Yasuto, 2014 .

A 250MHz 18Mb Full Ternary CAM with 0.3V Match Line Sense Amplifier in 65nm CMOS

Hayashi Isamu, Nii Koji, Kuroda Yasuto, 2013 .

A Router Architecture comprises plural components of Slice enabling Energy Consumption Reduction

Murata Masayuki, Ata Shingo, Hasegawa Go, 2011 .

Demonstration of 100 Gbps Optical Packet Switching using 16-bit Longest Prefix Matching Forwarding Engine

Harai Hiroaki, Kuroda Yasuto, Furukawa Hideaki, 2014 .

Low Energy Building Design in Packet Buffer Architecture with Deterministic Performance Guarantee

Ata Shingo, Oka Ikuo, Yamamoto Koji, 2009 .