Kin-Chu Ho

A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory

Hsie-Chia Chang, Chih-Lung Chen, Kin-Chu Ho, 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 3.46 Gb/s (9141,8224) LDPC-based ECC scheme and on-line channel estimation for solid-state drive applications

Hsie-Chia Chang, Chen-Yi Lee, Yen-Chin Liao, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Improving Read Performance of NAND Flash SSDs by Exploiting Error Locality

Ren-Shuo Liu, Chia-Lin Yang, Hsiang-Pang Li, 2016, IEEE Transactions on Computers.

A 45nm 6b/cell charge-trapping flash memory using LDPC-based ECC and drift-immune soft-sensing engine

Hsie-Chia Chang, Hsiang-Pang Li, Kin-Chu Ho, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

EC-Cache: Exploiting error locality to optimize LDPC in NAND flash-based SSDs

Ren-Shuo Liu, Chia-Lin Yang, Hsiang-Pang Li, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).