C. R. Moore

BANDWIDTH EFFICIENCY FOR DIGITAL COMMUNICATION VIA A HARD LIMITING CHANNEL

C. R. Cahn, C. R. Moore, 1972 .

Scalable hardware memory disambiguation for high-ILP processors

C. R. Moore, S. Keckler, R. Desikan, 2004, IEEE Micro.

Architecture for High Performance Systems

Vikas Agarwal, Karthikeyan Sankaralingam, Doug Burger, 2003 .

Exploiting ILP, TLP, and DLP with the polymorphous TRIPS architecture

C. R. Moore, S. Keckler, K. Sankaralingam, 2003, 30th Annual International Symposium on Computer Architecture, 2003. Proceedings..

Character string manipulation in APL

Charles R. Moore, C. R. Moore, 1974, APL '74.

Exploiting microarchitectural redundancy for defect tolerance

Doug Burger, Stephen W. Keckler, Premkishore Shivakumar, 2003, 2012 IEEE 30th International Conference on Computer Design (ICCD).

TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP

Jaehyuk Huh, Karthikeyan Sankaralingam, Doug Burger, 2004, TACO.

Microprocessor pipeline energy analysis

D. Burger, H. Hanson, C. R. Moore, 2003, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03..

Scalable hardware memory disambiguation for high-ILP processors

Simha Sethumadhavan, Doug Burger, Stephen W. Keckler, 2003, IEEE Micro.

Scaling to the end of silicon with EDGE architectures

Lizy Kurian John, Michael Dahlin, Kathryn S. McKinley, 2004, Computer.

Design considerations for the PowerPC 601 microprocessor

M. T. Vaden, L. J. Merkel, C. R. Moore, 1994, IBM J. Res. Dev..