K. Banerjee

Analytical modeling of single electron transistor for hybrid CMOS-SET analog IC design

S. Mahapatra, A.M. Ionescu, V. Vaish, 2004, IEEE Transactions on Electron Devices.

A global interconnect optimization scheme for nanometer scale VLSI with implications for latency, bandwidth, and power dissipation

K. Banerjee, Man Lung Mui, A. Mehrotra, 2004, IEEE Transactions on Electron Devices.