S. Paton

A continuous time low-pass sigma delta modulator implemented with transmission lines

E. Prefasi, L. Hernandez, P. Rombouts, 2005, SPIE Microtechnologies.

Optimization algorithm for linearity enhancement in the design of continuous-time sigma-delta modulators

S. Paton, A. Di Giandomenico, L. Hernandez, 2005, SPIE Microtechnologies.

Noise-shaping time-interleaved ADC based on a single ring oscillator and a sampling array

S. Paton, L. Hernandez, A. Quintero, 2017, 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS).

Interstage network to control overload in cascaded continuous-time /spl Sigma//spl Delta/ modulators

S. Paton, M. Sanchez-Renedo, 2007 .

A 12 bit Continuous-Time /spl Sigma//spl Delta/ modulator with 400MHz clock and low jitter sensitivity in 0.13 /spl mu/m CMOS

S. Paton, A. Wiesbauer, L. Hernandez, 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

A cascaded CT ΣΔ modulator with NTF zero and simple mismatch tuning method using interstage feedback

S. Paton, M. Sanchez-Renedo, 2007, 2007 Ph.D Research in Microelectronics and Electronics Conference.