Katsuhiko Shimabukuro

Design of a multiple-valued VLSI processor for digital control

Michitaka Kameyama, Tatsuo Higuchi, Katsuhiko Shimabukuro, 1992, [1992] Proceedings The Twenty-Second International Symposium on Multiple-Valued Logic.

Reconfigurable current-mode multiple-valued residue arithmetic circuits

Katsuhiko Shimabukuro, Chotei Zukeran, 1998, Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138).

VLSI Implementation of Current-Mode-Terminal Multiple-Valued Residue Arithmetic Circuits

Katsuhiko Shimabukuro, Chotei Zukeran, 1996 .

Architecture of a Parallel Multiple-Valued Arithmetic VLSI Processor Using Adder-Based Processing Elements (Special Issue on Multiple-Valued Integrated Circuits)

Michitaka Kameyama, Katsuhiko Shimabukuro, 1993 .

Speed-up of Neuromorphic Adiabatic Quantum Computation by Local Adiabatic Evolution

Katsuhiko Shimabukuro, Mitsunaga Kinjo, 2011, 2011 41st IEEE International Symposium on Multiple-Valued Logic.

Highly Parallel Residue Arithmetic Circuits Based on Barrel Shifters

Katsuhiko Shimabukuro, Chotei Zukeran, 1995 .

Multiple-valued mask-programmable logic array using one-transistor universal-literal circuits

Michitaka Kameyama, Takahiro Hanyu, Katsuhiko Shimabukuro, 2001, Proceedings 31st IEEE International Symposium on Multiple-Valued Logic.

Hardware Petri Nets on Programmable Devices

Morikazu Nakamura, Itaru Nagayama, Katsuhiko Shimabukuro, 2002 .