Naoki Ojima

A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion

Naoki Ojima, Toru Nakura, Tetsuya Iizuka, 2018, 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load

Naoki Ojima, Toru Nakura, Tetsuya Iizuka, 2018, VLSI-SoC.

A 0.0053-mm2 6-bit Fully-Standard-Cell-Based Synthesizable SAR ADC in 65 nm CMOS

Naoki Ojima, Tetsuya Iizuka, Zule Xu, 2019, 2019 17th IEEE International New Circuits and Systems Conference (NEWCAS).

Modeling method of element Rayleigh damping for the seismic analysis of a 3D FEM model with multiple damping properties

Naoki Ojima, Tadashi Iijima, Yuichi Ushio, 2018 .