Toru Nakura

发表

A Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion

Naoki Ojima, Toru Nakura, Tetsuya Iizuka, 2018, 2018 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

Buffer-ring-based all-digital on-chip monitor for PMOS and NMOS process variability and aging effects

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2010, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems.

A Pulse Width controlled PLL and its automated design flow

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2013, 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS).

Cascaded Time Difference Amplifier using Differential Logic Delay Cell

Makoto Ikeda, Toru Nakura, Kunihiro Asada, 2009, 2009 International SoC Design Conference (ISOCC).

Low pass filter-less pulse width controlled PLL with zero phase offset using pulse width accumulator

Toru Nakura, Kunihiro Asada, Tomohiko Yano, 2013, 2013 IEEE 20th International Conference on Electronics, Circuits, and Systems (ICECS).

Analytical design optimization of sub-ranging ADC based on stochastic comparator

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2016, 2016 IEEE International Test Conference (ITC).

All-digital PMOS and NMOS process variability monitor utilizing buffer ring with pulse counter

Makoto Ikeda, Toru Nakura, Tetsuya Iizuka, 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

Resonant Power Supply Noise Reduction by STO Capacitors Fabricated on Interposer

Toru Nakura, Kunihiro Asada, Masahiro Kano, 2015, IEICE Trans. Electron..

A 40-kS/s 16-bit non-binary SAR ADC in 0.18 CMOS with noise-tunable comparator

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2017, 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Measurement of power supply noise tolerance of self-timed processor

Makoto Ikeda, Toru Nakura, Kunihiro Asada, 2009, 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

On-chip di/dt Detector Circuit

Makoto Ikeda, Toru Nakura, Kunihiro Asada, 2005, IEICE Trans. Electron..

A 65 nm CMOS Synthesizable Digital Low-Dropout Regulator Based on Voltage-to-Time Conversion with 99.6% Current Efficiency at 10-mA Load

Naoki Ojima, Toru Nakura, Tetsuya Iizuka, 2018, VLSI-SoC.

Feedforward Active Substrate Noise Cancelling Based on di/dt of Power Supply

Makoto Ikeda, Toru Nakura, Kunihiro Asada, 2006, IEICE Trans. Electron..

Preliminary Experiments for Power Supply Noise Reduction Using On-Board Stubs

Makoto Ikeda, Toru Nakura, Kunihiro Asada, 2005, IEICE Trans. Electron..

Power integrity control of ATE for emulating power supply fluctuations on customer environment

Toru Nakura, Kunihiro Asada, Takashi Kusaka, 2012, 2012 IEEE International Test Conference.

LAGS System Using Data/Instruction Grain Power Control

Makoto Ikeda, Toru Nakura, Kunihiro Asada, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing

Toru Nakura, Kunihiro Asada, Takashi Kusaka, 2016, IEICE Trans. Electron..

A Technique for Analyzing On-Chip Power Supply Impedance

Toru Nakura, Kunihiro Asada, Rimon Ikeno, 2015, 2015 IEEE 24th Asian Test Symposium (ATS).

A Low Power and High Throughput Self Synchronous FPGA Using 65 nm CMOS with Throughput Optimization by Pipeline Alignment

Makoto Ikeda, Toru Nakura, Kunihiro Asada, 2010, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

7.5Vmax arbitrary waveform generator with 65nm standard CMOS under 1.2V supply voltage

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

Fully automated PLL compiler generating final GDS from specification

Toru Nakura, Kunihiro Asada, 2016, 2016 17th International Symposium on Quality Electronic Design (ISQED).

A 8bit two stage time-to-digital converter using time difference amplifier

Makoto Ikeda, Toru Nakura, Kunihiro Asada, 2010, IEICE Electron. Express.

Frequency Resolution Enhancement for Digitally-Controlled Oscillator Based on a Single-Period Switching Scheme

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2012, IEICE Trans. Electron..

Design, Analysis and Implementation of Pulse Generator by CMOS Flipped on Glass for Low Power UWB-IR

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

One week TAT of 0.8μm CMOS gate array with analog elements for educational exercise

Toru Nakura, Kunihiro Asada, Yuki Okamoto, 2016, 2016 11th European Workshop on Microelectronics Education (EWME).

CMOS-on-quartz pulse generator for low power applications

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

Low Pass Filter-Less Pulse Width Controlled PLL Using Time to Soft Thermometer Code Converter

Toru Nakura, Kunihiro Asada, 2012, IEICE Trans. Electron..

Triangular Active Charge Injection Method for Resonant Power Supply Noise Reduction

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2018, IEICE Trans. Electron..

A 16-bit 2.0-ps Resolution Two-Step TDC in 0.18- $\mu$ m CMOS Utilizing Pulse-Shrinking Fine Stage With Built-In Coarse Gain Calibration

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2019, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Resonant power supply noise reduction using a triangular active charge injection

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).

High Spatial Resolution Detection Method for Point Light Source in Scintillator

Kai Xu, Toru Nakura, Tetsuya Iizuka, 2017, Computational Imaging.

All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance

Makoto Ikeda, Toru Nakura, Kunihiro Asada, 2009, 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

1.0 ps Resolution Time-to-Digital Converter Based-On Cascaded Time-Difference-Amplifier Utilizing Differential Logic Delay Cells

Makoto Ikeda, Toru Nakura, Tetsuya Iizuka, 2011, IEICE Trans. Electron..

A 4-cycle-start-up reference-clock-less all-digital burst-mode CDR based on cycle-lock gated-oscillator with frequency tracking

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2016, ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference.

A calibration-free time difference accumulator using two pulses propagating on a single buffer ring

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2015, 2015 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2017, IEICE Trans. Electron..

Impulse signal generator based on current-mode excitation and transmission line resonator

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2017, 2017 15th IEEE International New Circuits and Systems Conference (NEWCAS).

On-Chip Resonant Supply Noise Canceller Utilizing Parasitic Capacitance of Sleep Blocks for Power Mode Switch

Makoto Ikeda, Toru Nakura, Kunihiro Asada, 2011, IEICE Trans. Electron..

A triangular active charge injection scheme using a resistive current for resonant power supply noise suppression

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2017, 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

An Asynchronous Summation Circuit for Noise Filtering in Single Photon Avalanche Diode Sensors

Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, 2016, J. Circuits Syst. Comput..

Time Difference Amplifier with Robust Gain Using Closed-Loop Control

Makoto Ikeda, Toru Nakura, Kunihiro Asada, 2010, IEICE Trans. Electron..

A fine-resolution pulse-shrinking time-to-digital converter with completion detection utilizing built-in offset pulse

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Numerical and theoretical analysis on voltage and time domain dynamic range of scaled CMOS circuits

Toru Nakura, Kunihiro Asada, Kevin Ngari Muriithi, 2014, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

A 15 × 15 SPAD array sensor with breakdown-pixel-extraction architecture for efficient data readout

Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, 2017, 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).

On-chip resonant supply noise reduction utilizing switched parasitic capacitors of sleep blocks with tri-mode power gating structure

Makoto Ikeda, Toru Nakura, Kunihiro Asada, 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

Impact of All-Digital PLL on SoC Testing

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2012, 2012 IEEE 21st Asian Test Symposium.

Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing

Toru Nakura, Kunihiro Asada, Takashi Kusaka, 2016, J. Electron. Test..

On-Chip Switched Parasitic Capacitors of Sleep Blocks for Resonant Supply Noise Reduction

Makoto Ikeda, Toru Nakura, Kunihiro Asada, 2012, IEICE Trans. Electron..

Extension of power supply impedance emulation method on ATE for multiple power domain

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2017, 2017 22nd IEEE European Test Symposium (ETS).

Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops

Toru Nakura, Koichi Nose, Masayuki Mizuno, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

An ultra-wide-range fine-resolution two-step time-to-digital converter with built-in foreground coarse gain calibration

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2017, 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Tracking PVT variations of Pulse Width Controlled PLL using variable-length ring oscillator

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2015, 2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC).

Decoupling capacitance boosting for on-chip resonant supply noise reduction

Makoto Ikeda, Toru Nakura, Kunihiro Asada, 2011, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems.

On-Chip Switched Decoupling Capacitor for Fast Voltage Hopping of DVS Systems

Makoto Ikeda, Toru Nakura, Kunihiro Asada, 2013, IEICE Trans. Electron..

Analysis and design of a triangular active charge injection for stabilizing resonant power supply noise

Toru Nakura, Kunihiro Asada, Masahiro Kano, 2016, 2016 17th International Symposium on Quality Electronic Design (ISQED).

Design of Active Substrate Noise Canceller using Power Supply di/dt Detector

Makoto Ikeda, Toru Nakura, Kunihiro Asada, 2007, 2007 Asia and South Pacific Design Automation Conference.

Stress-balance Flip-Flops for NBTI tolerant circuit based on Fine-Grain Redundancy

Toru Nakura, Kunihiro Asada, Teruki Nakasato, 2011, 2011 International SoC Design Conference.

Stub vs. Capacitor for Power Supply Noise Reduction

Makoto Ikeda, Toru Nakura, Kunihiro Asada, 2005, IEICE Trans. Electron..

Comparative study of RF energy harvesting rectifiers and proposal of output voltage universal curves for design guidline

Toru Nakura, Kunihiro Asada, Hiroaki Matsui, 2015, IEICE Electron. Express.

A PLL Compiler from Specification to GDSII

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2017, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

A compact quick-start sub-mW pulse-width-controlled PLL with automated layout synthesis using a place-and-route tool

Toru Nakura, Tetsuya Iizuka, Zule Xu, 2019, IEICE Electron. Express.

All-Digital On-Chip Monitor for PMOS and NMOS Process Variability Utilizing Buffer Ring with Pulse Counter

Makoto Ikeda, Toru Nakura, Tetsuya Iizuka, 2011, IEICE Trans. Electron..

Optimal Design Method of Sub-Ranging ADC Based on Stochastic Comparator

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2018, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

Quick-Start Pulse Width Controlled PLL with Frequency and Phase Presetting

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2018, IEICE Trans. Electron..

An On-Chip Measurement of PLL Transfer Function and Lock Range through Fully Digital Interface

Toru Nakura, Kunihiro Asada, Toshiyuki Kikkawa, 2016, IEICE Trans. Electron..

Time-domain approach for analog circuits in deep sub-micron LSI

Makoto Ikeda, Toru Nakura, Tetsuya Iizuka, 2018, IEICE Electron. Express.

An all-digital time difference hold-and-replication circuit utilizing a dual pulse ring oscillator

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

Moebius circuit: dual-rail dynamic logic for logic gate level pipeline with error gate search feature

Makoto Ikeda, Toru Nakura, Kunihiro Asada, 2009, GLSVLSI '09.

Dual Imager Core Chip with 24.8 Rangemaps/s 3-D and 58 fps 2-D Simultaneous Capture Capability

Makoto Ikeda, Toru Nakura, Kunihiro Asada, 2009, IEICE Trans. Electron..

Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills

Toru Nakura, Kunihiro Asada, Takashi Kusaka, 2014, 2014 International Test Conference.

An Asynchronous Projection and Summation Circuit for In-Pixel Processing in Single Photon Avalanche Diode Sensors

Hongbo Zhu, Toru Nakura, Tetsuya Iizuka, 2015, 2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2018, J. Electron. Test..

Burst-pulse Generator based on transmission line toward sub-MMW

Toru Nakura, Kunihiro Asada, Nguyen Ngoc Mai Khanh, 2014, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems.

Autonomous di/dt Control of Power Supply for Margin Aware Operation

Makoto Ikeda, Toru Nakura, Kunihiro Asada, 2006, IEICE Trans. Electron..

LAPAREX-An Automatic Parameter Extraction Program for Gain- and Index-Coupled Distributed Feedback Semiconductor Lasers, and Its Application to Observation of Changing Coupling Coefficients with Currents

Yoshiaki Nakano, Toru Nakura, 2000 .

Resonant power supply noise reduction using on-die decoupling capacitors embedded in organic interposer

Toru Nakura, Kunihiro Asada, Masahiro Kano, 2014, 2014 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS).

A SPAD array sensor based on breakdown pixel extraction architecture with background readout for scintillation detector

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2017, 2017 IEEE SENSORS.

A 15 × 15 single photon avalanche diode sensor featuring breakdown pixels extraction architecture for efficient data readout

Toru Nakura, Tetsuya Iizuka, Kunihiro Asada, 2016 .

Ring oscillator based random number generator utilizing wake-up time uncertainty

Toru Nakura, Kunihiro Asada, Makoto Ikeda, 2009, 2009 IEEE Asian Solid-State Circuits Conference.

A 8bit two stage time-to-digital converter using 16x cascaded time difference amplifier in 0.18um CMOS

Toru Nakura, Kunihiro Asada, Shingo Mandai, 2010, Melecon 2010 - 2010 15th IEEE Mediterranean Electrotechnical Conference.