Philippe Candelier

发表

Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model

Giorgio Di Natale, Régis Leveugle, Jean-Max Dutertre, 2018, 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC).

Laser-induced fault effects in security-dedicated circuits

Giorgio Di Natale, Régis Leveugle, Jean-Max Dutertre, 2014, 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC).

Power supply glitch attacks: Design and evaluation of detection circuits

Assia Tria, Jean-Baptiste Rigaud, Philippe Candelier, 2014, 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST).

Clock generator behavioral modeling for supply voltage glitch attack effects analysis

Vincent Beroulle, David Hély, Philippe Candelier, 2016, Microprocess. Microsystems.

Increasing the security level of analog IPs by using a dedicated vulnerability analysis methodology

Vincent Beroulle, David Hély, Philippe Candelier, 2013, International Symposium on Quality Electronic Design (ISQED).

Modeling of OxRAM variability from low to high resistance state using a stochastic trap assisted tunneling-based resistor network

Gerard Ghibaudo, Elisa Vianello, Philippe Candelier, 2015, EUROSOI-ULIS 2015: 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon.

Evaluating and Enhancing the Security of Analog and Mixed IPs in Complex System On Chip

Vincent Beroulle, Philippe Candelier, Kamil Gomina, 2013 .

Extended TDDB power-law validation for high-voltage applications such as OTP memories in High-k CMOS 28nm FDSOI technology

Bruno Allard, X. Federspiel, S. Denorme, 2015, 2015 IEEE International Reliability Physics Symposium.

Laser-induced fault effects in security-dedicated circuits

Giorgio Di Natale, Régis Leveugle, Jean-Max Dutertre, 2014, VLSI-SoC.

Voltage Glitch Attacks on Mixed-Signal Systems

Assia Tria, Vincent Beroulle, David Hély, 2014, 2014 17th Euromicro Conference on Digital System Design.

Modelling of the 1T-Bulk capacitor-less DRAM cell with improved performances: The way to scaling

R. Ranica, R. Bouchakour, Pascale Mazoyer, 2005 .

Cell memory technology has unique programming cmos

Philippe Candelier, Jean Pierre Schoellkopf, 1998 .

On the impact of OxRAM-based synapses variability on convolutional neural networks performance

Elisa Vianello, Olivier Bichler, Christian Gamrat, 2015, Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH´15).

Review of fuse and antifuse solutions for advanced standard CMOS technologies

Bruno Allard, Philippe Candelier, Elodie Ebrard, 2009, Microelectronics Journal.

Power analysis methodology for secure circuits

Assia Tria, Jean-Baptiste Rigaud, Philippe Candelier, 2013, 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS).

Method of manufacturing an anti-fuse memory point

Philippe Candelier, Roux Elise Le, 2010 .

Detecting positive voltage attacks on CMOS circuits

Assia Tria, Jean-Baptiste Rigaud, Philippe Candelier, 2014, CS2 '14.

Benefit of Al2O3/HfO2 bilayer for BEOL RRAM integration through 16kb memory cut characterization

Elisa Vianello, S. Denorme, Philippe Candelier, 2015, 2015 45th European Solid State Device Research Conference (ESSDERC).

Resistive memory variability: A simplified trap-assisted tunneling model

B. DeSalvo, Elisa Vianello, Philippe Candelier, 2016 .

Application of a TDDB Model to the Optimization of the Programming Voltage and Dimensions of Antifuse Bitcells

Bruno Allard, Philippe Candelier, Matthieu Deloge, 2011, IEEE Electron Device Letters.

Antifuse bitcell array design methodology driven by reliability study in 45nm

Bruno Allard, Philippe Candelier, Elodie Ebrard, 2009, 2009 Proceedings of the European Solid State Device Research Conference.

Laser attacks on integrated circuits: From CMOS to FD-SOI

Giorgio Di Natale, Jean-Max Dutertre, Bruno Rouzeyre, 2014, 2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

cells making method memories of type a single programming having MOS capacitors and integrated circuit corresponding

Stephane Denorme, Philippe Candelier, 2015 .

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks

Giorgio Di Natale, Régis Leveugle, Jean-Max Dutertre, 2018, 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS).

Improvement of performances HfO 2 -based RRAM from elementary cell to 16 kb demonstrator by introduction of thin layer of Al 2 O 3

Claire Fenouillet-Beranger, Stephane Denorme, Elisa Vianello, 2016 .

Mechanisms of charge modulation in the floating body of triple-well nMOSFET capacitor-less DRAMs

R. Ranica, Thomas Skotnicki, Sorin Cristoloveanu, 2004 .

Experimental and theoretical investigation of nonvolatile memory data-retention

G. Reimbold, Gerard Ghibaudo, G. Pananakakis, 1999 .

Understanding the influence of antifuse bitcell dimensions the programming time and energy using an analytical model

Bruno Allard, Philippe Candelier, Joel Damiens, 2010, 2010 IEEE International Integrated Reliability Workshop Final Report.