Athanasios Papadimitriou

发表

Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model

Giorgio Di Natale, Régis Leveugle, Jean-Max Dutertre, 2018, 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography (FDTC).

Laser-induced fault effects in security-dedicated circuits

Giorgio Di Natale, Régis Leveugle, Jean-Max Dutertre, 2014, 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC).

On the Importance of Analysing Microarchitecture for Accurate Software Fault Models

Vincent Beroulle, Johan Laurent, Christophe Deleuze, 2018, 2018 21st Euromicro Conference on Digital System Design (DSD).

A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks

Vincent Beroulle, Regis Leveugle, Athanasios Papadimitriou, 2014, DATE 2014.

Laser-induced fault effects in security-dedicated circuits

Giorgio Di Natale, Régis Leveugle, Jean-Max Dutertre, 2014, VLSI-SoC.

On the Performance of Non-Profiled Differential Deep Learning Attacks against an AES Encryption Algorithm Protected using a Correlated Noise Generation based Hiding Countermeasure

Vincent Beroulle, Athanasios Papadimitriou, Amir Alipour, 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

On a Side Channel and Fault Attack Concurrent Countermeasure Methodology for MCU-based Byte-sliced Cipher Implementations

David Hely, Athanasios Papadimitriou, Ehsan Aerabi, 2019, 2019 IEEE 25th International Symposium on On-Line Testing and Robust System Design (IOLTS).

A multiple fault injection methodology based on cone partitioning towards RTL modeling of laser attacks

Régis Leveugle, Vincent Beroulle, Paolo Maistri, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

RTL modeling of laser attacks for early evaluation of secure ICs and countermeasure design

Athanasios Papadimitriou, 2016 .

On the development of a new countermeasure based on a laser attack RTL fault model

Régis Leveugle, Vincent Beroulle, Paolo Maistri, 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

On fault injections for early security evaluation vs. laser-based attacks

Régis Leveugle, Vincent Beroulle, Paolo Maistri, 2016, 2016 1st IEEE International Verification and Security Workshop (IVSW).

Design Space Exploration for Ultra-Low Energy and Secure IoT MCUs

David Hély, Mahdi Fazeli, Athanasios Papadimitriou, 2020 .

On a Low Cost Fault Injection Framework for Security Assessment of Cyber-Physical Systems: Clock Glitch Attacks

Vincent Beroulle, David Hely, Athanasios Papadimitriou, 2019, 2019 IEEE 4th International Verification and Security Workshop (IVSW).

FPGA emulation of laser attacks against secure deep submicron integrated circuits

Vincent Beroulle, Paolo Maistri, Regis Leveugle, 2013 .

Cross-layer analysis of software fault models and countermeasures against hardware fault attacks in a RISC-V processor

Vincent Beroulle, Johan Laurent, Christophe Deleuze, 2019, Microprocess. Microsystems.

Comparison of RTL fault models for the robustness evaluation of aerospace FPGA devices

Vincent Beroulle, David Hély, Athanasios Papadimitriou, 2016, 2016 IEEE 22nd International Symposium on On-Line Testing and Robust System Design (IOLTS).

Analysis of laser-induced errors: RTL fault models versus layout locality characteristics

Régis Leveugle, Vincent Beroulle, Paolo Maistri, 2016, Microprocess. Microsystems.

Hardware Security Evaluation Platform for MCU-Based Connected Devices: Application to Healthcare IoT

Mahdi Fazeli, Vincent Beroulle, David Hély, 2018, 2018 IEEE 3rd International Verification and Security Workshop (IVSW).

CONFISCA : an SIMD-based CONcurrent FI and SCA countermeasure with switchable performance and security modes

David Hély, Mahdi Fazeli, Athanasios Papadimitriou, 2020, IACR Cryptol. ePrint Arch..

Can Algorithm Diversity in Stream Cipher Implementation Thwart (Natural and) Malicious Faults?

Ramesh Karri, Chi Zhang, Chenglu Jin, 2016, IEEE Transactions on Emerging Topics in Computing.

On error models for RTL security evaluations

Régis Leveugle, Vincent Beroulle, Paolo Maistri, 2014, 2014 9th IEEE International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS).

Validation of RTL laser fault injection model with respect to layout information

Régis Leveugle, Vincent Beroulle, Paolo Maistri, 2015, 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

Stack Redundancy to Thwart Return Oriented Programming in Embedded Systems

Thomas Meyer, Athanasios Papadimitriou, Cyril Bresch, 2018, IEEE Embedded Systems Letters.

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks

Giorgio Di Natale, Régis Leveugle, Jean-Max Dutertre, 2018, 2018 IEEE 24th International Symposium on On-Line Testing And Robust System Design (IOLTS).

Analyzing the Single Event Upset Vulnerability of Binarized Neural Networks on SRAM FPGAs

Mihalis Psarakis, Vasileios Vlagkoulis, Aitzan Sari, 2021, 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

Analyzing the Impact of Approximate Adders on the Reliability of FPGA Accelerators

Mihalis Psarakis, Athanasios Papadimitriou, Ioannis Tsounis, 2021, 2021 IEEE European Test Symposium (ETS).