K. Takeuchi

A Split-Level Diagonal Bit-line (SLDB) stacked capacitor cell for 256 Mb DRAMs

N. Tanabe, S. Ohya, H. Hada, 1992, 1992 International Technical Digest on Electron Devices Meeting.

45-nm gate length CMOS technology and beyond using steep halo

T. Fukai, H. Wakabayashi, T. Matsuda, 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

High performance 50-nm physical gate length pMOSFETs by using low temperature activation by re-crystallization scheme

T. Mogami, K. Takeuchi, K. Tsuji, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

Analysis and prospect of local variability of drain current in scaled MOSFETs by a new decomposition method

A. Kumar, T. Hiramoto, S. Inaba, 2010, 2010 Symposium on VLSI Technology.

Suppression of VT variability degradation induced by NBTI with RDF control

A. Kumar, T. Hiramoto, S. Inaba, 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.

A 0.10-/spl mu/m CMOS device with a 40-nm gate sidewall and multilevel interconnects for system LSI

T. Fukai, H. Wakabayashi, Y. Nakahara, 1999, 1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325).

A new methodology for evaluating VT variability considering dopant depth profile

T. Hiramoto, S. Inaba, S. Kamohara, 2006, 2009 Symposium on VLSI Technology.

Sub-10-nm planar-bulk-CMOS devices using lateral junction control

A. Ogura, H. Wakabayashi, T. Mogami, 2003, IEEE International Electron Devices Meeting 2003.

Characteristics and Modeling of Sub-10-nm Planar Bulk CMOS Devices Fabricated by Lateral Source/Drain Junction Control

H. Kawaura, H. Wakabayashi, M. Hane, 2006, IEEE Transactions on Electron Devices.