H. M. Shao

发表

A VLSI single chip 8-bit finite field multiplier

Trieu-Kien Truong, L. J. Deutsch, H. M. Shao, 1985 .

A parallel VLSI architecture for a digital filter using a number theoretic transform

Trieu-Kien Truong, H. M. Shao, I. S. Reed, 1983 .

A Parallel VLSI (Very Large Scale Integration) Architecture for a Digital Filter Using a Number Theorectic Transform

H. M. Shao, I. S. Reed, T. K. Truong, 1983 .

Systolic VLSI Reed-Solomon Decoder

J. H. Yuen, Trieu-Kien Truong, L. J. Deutsch, 1986 .

Multiplier Architecture for Coding Circuits

C. C. Wang, L. J. Deutsch, H. M. Shao, 1986 .

A parallel VLSI architecture for a digital filter of arbitrary length using Fermat number transforms

H. M. Shao, I. S. Reed, T. K. Truong, 1982 .

A Systolic VLSI Design of a Pipeline Reed-solomon Decoder

J. H. Yuen, L. J. Deutsch, H. M. Shao, 1984 .

A single VLSI chip for computing syndromes in the (225, 223) Reed-Solomon decoder

L. J. Deutsch, H. M. Shao, I. S. Hsu, 1986 .

A New CT-Aided Robotic Stereotaxis System.

H. M. Shao, I. S. Reed, J. Y. Chen, 1985 .

The design plan of a VLSI single chip (255, 223) Reed-Solomon decoder

L. J. Deutsch, H. M. Shao, I. S. Hsu, 1987 .

Fast polynomial transform and its implementation by computer

Trieu-Kien Truong, Irving S. Reed, H. M. Shao, 1981 .

A New CT-Aided Stereotactic Neurosurgery Technique

H. M. Shao, I. S. Reed, I. Reed, 1985, IEEE Transactions on Biomedical Engineering.