Keng L. Wong

Interpolated VCO design for a low bandwidth, low-jitter, self-biased PLL in 45 nm CMOS

Greg Taylor, David E. Duarte, Suching Hsu, 2010, IEEE Custom Integrated Circuits Conference 2010.

Apparatus for power management of an integrated circuit device

Keng L. Wong, Kelly J. Fitzpatrick, Jeffrey E. Smith, 1994 .

A PLL clock generator with 5 to 110 MHz of lock range for microprocessors

Keng L. Wong, I. A. Young, J. K. Greason, 1992 .

Advanced thermal sensing circuit and test techniques used in a high performance 65nm processor

Greg Taylor, Usman Mughal, David E. Duarte, 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

Temperature Sensor Design in a High Volume Manufacturing 65nm CMOS Digital Process

Greg Taylor, Usman Mughal, David E. Duarte, 2007, 2007 IEEE Custom Integrated Circuits Conference.

High Performance Microprocessor

Feng Wang, Keng L. Wong, Ernest Knoll, 2003 .

A 150 MHz 0.6 /spl mu/m BiCMOS superscalar microprocessor

Goutam Debnath, Keng L. Wong, Lawrence T. Clark, 1994 .

A high performance 0.35-/spl mu/m 3.3-V BiCMOS technology optimized for product porting from a 0.6-/spl mu/m 3.3-V BiCMOS technology

Keng L. Wong, George L. Geannopoulos, Jashojiban Banik, 1996 .

A PLL clock generator with 5 to 110 MHz lock range for microprocessors

Keng L. Wong, I. Young, J. Greason, 1992, 1992 IEEE International Solid-State Circuits Conference Digest of Technical Papers.