Chrong Jung Lin

发表

A 65-nm ReRAM-Enabled Nonvolatile Processor With Time-Space Domain Adaption and Self-Write-Termination Achieving > 4× Faster Clock Frequency and > 6× Higher Restore Speed

Meng-Fan Chang, Huazhong Yang, Yongpan Liu, 2017, IEEE J. Solid State Circuits.

A ReRAM-based single-NVM nonvolatile flip-flop with reduced stress-time and write-power against wide distribution in write-time by using self-write-termination scheme for nonvolatile processors in IoT era

Meng-Fan Chang, Huazhong Yang, Yongpan Liu, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Memory-Logic Hybrid Gate with 3D-Stackable Complementary Latches for FinFET-based Neural Networks

Yue-Der Chih, Ya-Chin King, Chrong Jung Lin, 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

High‐uniformity 2T1C AMOLED panels by a built‐in trimming method

Chrong Jung Lin, Ya-Chin King, Te-Yu Lee, 2010 .

On-chip trimming circuit based on embedded one-time-programming memory for magnetic wireless interlayer transmission module

Ming-Jinn Tsai, Ya-Chin King, Chrong Jung Lin, 2015 .

FinFET CMOS logic gates with non-volatile states for reconfigurable computing systems

Yue-Der Chih, Jonathan Chang, Ya-Chin King, 2019, Integr..

A High-Density MTP Cell With Contact Coupling Gates by Pure CMOS Logic Process

Chrong Jung Lin, Cheng-Wei Tsai, Haw-Yun Wu, 2011, IEEE Electron Device Letters.

Variable-length gateless transistor for analog one-time-programmable memory applications

Ya-Chin King, Chrong Jung Lin, Po-Ruei Cheng, 2016, 2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

A New Differential P-Channel Logic-Compatible Multiple-Time Programmable (MTP) Memory Cell With Self-Recovery Operation

Ya-Chin King, Chrong Jung Lin, Chiu-Wang Lien, 2011, IEEE Electron Device Letters.

A Study of Self-Aligned Nitride Erasable OTP Cell by 45-nm CMOS Fully Compatible Process

Chia-En Huang, Ya-Chin King, Chrong Jung Lin, 2009, IEEE Transactions on Electron Devices.

Electron trapping effect on the switching behavior of contact RRAM devices through random telegraph noise analysis

Chia-En Huang, Ya-Chin King, Chrong Jung Lin, 2010, 2010 International Electron Devices Meeting.

Statistical analysis of the correlations between cell performance and its initial states in contact resistive random access memory cells

Ya-Chin King, Chrong Jung Lin, Yun Feng Kao, 2017 .

High-K metal gate contact RRAM (CRRAM) in pure 28nm CMOS logic process

Ming-Jinn Tsai, Ya-Chin King, Shyh-Shyuan Sheu, 2012, 2012 International Electron Devices Meeting.

Real-Time Variable-Resolution and Dynamic Range Boosting CMOS Image Sensor

Chrong Jung Lin, Ya-Chin King, Jian-Jie Wang, 2007 .

Pinch-Off Voltage-Adjustable High-Voltage Junction Field-Effect Transistor

Chrong Jung Lin, Chorng-Wei Liaw, Leaf Yeh, 2007, IEEE Electron Device Letters.

P-17: High-Uniformity 2T1C AMOLED Panels by Using a New Built-In Trimming Method

Chih-Chung Liu, Chrong Jung Lin, Ya-Chin King, 2009 .

3D time-contingent physical unclonable function array on 16nm FinFET dielectric RRAM

Yue-Der Chih, Ya-Chin King, Chrong Jung Lin, 2017, 2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM).

A new laterally conductive bridge random access memory by fully CMOS logic compatible process

Yu-Cheng Lin, Ming-Jinn Tsai, Yu-Der Chih, 2014 .

Twin-Bit Resistive Random Access Memory in FinFET CMOS Logic Technologies

Ya-Chin King, Chrong Jung Lin, Chieh Lee, 2019, 2019 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Memristor Logic Operation Gate With Share Contact RRAM Cell

Chrong Jung Lin, Y.-D Chih, Yuan Heng Tseng, 2011, IEEE Electron Device Letters.

Mapping of wafer-level plasma induced charge contour by novel on-chip in-situ recorders in advance FinFET technologies

Ya-Chin King, Chrong Jung Lin, Chun-Hsiung Wu, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Twin mode NV logic gates for high speed computing system on 16nm FINFET CMOS logic process

Yue-Der Chih, Ya-Chin King, Chrong Jung Lin, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

A New High-Density and Ultrasmall-Cell-Size Contact RRAM (CR-RAM) With Fully CMOS-Logic-Compatible Technology and Circuits

Chia-En Huang, Ya-Chin King, Chrong Jung Lin, 2011, IEEE Transactions on Electron Devices.

4.7 A 65nm ReRAM-enabled nonvolatile processor with 6× reduction in restore time and 4× higher clock frequency using adaptive data retention and self-write-termination nonvolatile logic

Yu Wang, Meng-Fan Chang, Qi Wei, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process

Ya-Chin King, Chrong Jung Lin, Meng-Yin Hsu, 2017, Nanoscale Research Letters.

Zero static-power 4T SRAM with self-inhibit resistive switching load by pure CMOS logic process

Yue-Der Chih, Ya-Chin King, Chrong Jung Lin, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

7.4 A 256b-wordlength ReRAM-based TCAM with 1ns search-time and 14× improvement in wordlength-energyefficiency-density product using 2.5T1R cell

Meng-Fan Chang, Tien-Fu Chen, Ya-Chin King, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

New High-Density Differential Split Gate Flash Memory With Self-Boosting Function

Yue-Der Chih, Chrong Jung Lin, Ya-Chin King, 2013, IEEE Electron Device Letters.

28-nm 2T High-$K$ Metal Gate Embedded RRAM With Fully Compatible CMOS Logic Processes

Frederick T. Chen, Ming-Jinn Tsai, Yue-Der Chih, 2013, IEEE Electron Device Letters.

High Sensitivity of Dielectric films Structure for Advanced CMOS Image Sensor Technology

Dun-Nian Yaung, Chung S. Wang, Chrong Jung Lin, 2007 .

Multi-channel magnetic transmission interface for 3D contactless connection

Ming-Jinn Tsai, Ya-Chin King, Chrong Jung Lin, 2015, 2015 International Symposium on VLSI Technology, Systems and Applications.

Self-convergent trimming of embedded logic compatible OTP memory for VT variation reduction in low voltage SRAMs

Hung-Yu Chen, Ya-Chin King, Chrong Jung Lin, 2014, Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

Challenges and Circuit Techniques for Energy-Efficient On-Chip Nonvolatile Memory Using Memristive Devices

Meng-Fan Chang, Albert Lee, Ya-Chin King, 2015, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

Gate and Read Disturb Failure Mechanisms in Source-Side Erased Flash EEPROM Memory Cell

Charles Ching-Hsiang Hsu, Chrong Jung Lin, Hsin-Ming Chen, 1998 .

A New Self-Aligned Nitride MTP Cell with 45nm CMOS Fully Compatible Process

Chia-En Huang, Chrong Jung Lin, Hsin-Ming Chen, 2007, 2007 IEEE International Electron Devices Meeting.

A Highly Scalable Interface Fuse for Advanced CMOS Logic Technologies

Chrong Jung Lin, Min-Che Hsieh, Yung-Wen Chin, 2012, IEEE Electron Device Letters.

Investigation of Set/Reset Operations in CMOS-Logic-Compatible Contact Backfilled RRAMs

Hung-Yu Chen, Ya-Chin King, Chrong Jung Lin, 2016, IEEE Transactions on Device and Materials Reliability.

Multilevel Anti-Fuse Cells by Progressive Rupturing of the High- $\kappa $ Gate Dielectric in FinFET Technologies

Ya-Chin King, Chrong Jung Lin, Yu-Zheng Chen, 2016, IEEE Electron Device Letters.

Low ${\rm VDDmin}$ Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against Resistance and Switch-Time Variations

Meng-Fan Chang, Yen-Chen Liu, Yu-Der Chih, 2015, IEEE Journal of Solid-State Circuits.

A New 2T Contact Coupling Gate MTP Memory in Fully CMOS Compatible Process

Yue-Der Chih, Chrong Jung Lin, Cheng-Wei Tsai, 2012, IEEE Transactions on Electron Devices.

45nm Gateless Anti-Fuse Cell with CMOS Fully Compatible Process

Chrong Jung Lin, Hsin-Ming Chen, Ya-Chin King, 2007, 2007 IEEE International Electron Devices Meeting.

Twin-bit Via RRAM in 16nm FinFET Logic Technologies

Ya-Chin King, Chrong Jung Lin, Y.-H. Shih, 2017 .

Characterization and optimization of NO-nitrided gate oxide by RTP

Chrong Jung Lin, S.C. Sun, C. H. Chen, 1995, Proceedings of International Electron Devices Meeting.

A CMOS Active Pixel Sensor With Light Intensity Filtering Characteristics for Image Thresholding Application

Chrong Jung Lin, C. Lin, C. Huang, 2012, IEEE Sensors Journal.

Three-Dimensional $\hbox{4F}^{2}$ ReRAM With Vertical BJT Driver by CMOS Logic Compatible Process

Heng-Yuan Lee, Ming-Jinn Tsai, Ya-Chin King, 2011, IEEE Transactions on Electron Devices.

Magnetic Wireless Interlayer Transmission Through Perpendicular MTJ for 3-D IC Applications

Ming-Jinn Tsai, Ya-Chin King, Chrong Jung Lin, 2014, IEEE Transactions on Electron Devices.

High program efficiency of p-type floating gate in n-channel split-gate embedded flash memory

Ya-Chin King, Chrong Jung Lin, An-Chi Kang, 2008 .

Integrated ambient light sensor in LTPS LCD panel with silicon nanocrystals photosensor

Ya-Chin King, Chrong Jung Lin, Wen-Jen Chiang, 2007 .

Embedded Optical Sensor Using Gate-Body-Tied Thin-Film Transistor on Low-Temperature Poly-Silicon Display Panel

Ya-Chin King, Chrong Jung Lin, Wen-Jen Chiang, 2009 .

A novel high-density embedded AND-type split gate flash memory

Ya-Chin King, Chrong Jung Lin, Chiu-Wang Lien, 2014 .

Point twin-bit RRAM in 3D interweaved cross-point array by Cu BEOL process

Ya-Chin King, Chrong Jung Lin, Min-Che Hsieh, 2014, 2014 IEEE International Electron Devices Meeting.

High Resolution Ion Detector (HRID) by 16nm FinFET CMOS Technology

Peng-Chun Liou, Yu-Lun Chueh, Jonathan Chang, 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

Modeling of electron conduction in contact resistive random access memory devices as random telegraph noise.

Chrong Jung Lin, Yuan Heng Tseng, Wen Chao Shen, 2012, Journal of applied physics.