Peter Hallschmid

Fast design space exploration for low-power configurable processors

Peter Hallschmid, P. Hallschmid, 2008 .

Detailed routing architectures for embedded programmable logic IP cores

Steven J. E. Wilton, Peter Hallschmid, S. Wilton, 2001, FPGA '01.

Routing architecture optimizations for high-density embedded programmable IP cores

Steven J. E. Wilton, Peter Hallschmid, S. Wilton, 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fast configuration of an energy-efficient branch predictor

Resve A. Saleh, Peter Hallschmid, R. Saleh, 2006, IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures (ISVLSI'06).

Modeling and Evaluation of Dynamic Partial Reconfigurable Datapaths for FPGA-Based Systems Using Stochastic Networks

Rehan Ahmed, Peter Hallschmid, P. Hallschmid, 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

Automatic Cache Tuning for Energy-Efficiency using Local Regression Modeling

Resve A. Saleh, Peter Hallschmid, 2007, 2007 44th ACM/IEEE Design Automation Conference.

High-level synthesis-based design methodology for Dynamic Power-Gated FPGAs

Steven J. E. Wilton, Rehan Ahmed, Peter Hallschmid, 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

Hierarchical Dynamic Power-Gating in FPGAs

Steven J. E. Wilton, Rehan Ahmed, Peter Hallschmid, 2015, ARC.

Model-based Performance Evaluation of Dynamic Partial Reconfigurable Datapaths for FPGA-based Systems

Rehan Ahmed, Peter Hallschmid, 2013 .

Local congestion and blockage aware routability analysis using adaptive flexible modeling

André Ivanov, Peter Hallschmid, Zhonghua Zhou, 2016, 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS).

Fast Design Space Exploration Using Local Regression Modeling With Application to ASIPs

Resve A. Saleh, Peter Hallschmid, R. Saleh, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.