H.-S. Philip Wong

发表

Metal–Oxide RRAM

Shimeng Yu, H.-S. Philip Wong, Heng-Yuan Lee, 2012, Proceedings of the IEEE.

RRAM based synaptic devices for neuromorphic visual systems

Shimeng Yu, H.-S. Philip Wong, Peng Huang, 2015, 2015 IEEE International Conference on Digital Signal Processing (DSP).

Dilute phosphide nitride materials as photocathodes for electrochemical solar energy conversion

H.-S. Philip Wong, Vijay Parameshwaran, Xiaoqing Xu, 2013, Photonics West - Optoelectronic Materials and Devices.

Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE model

Y. Wu, H.-S. Philip Wong, Peng Huang, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Nanotechnology 101 Part 1

H.-S. Philip Wong, 2006 .

Carbon nanotube transistor compact model for circuit design and performance optimization

H.-S. Philip Wong, Jie Deng, Albert Lin, 2008, JETC.

Brain-like associative learning using a nanoscale non-volatile phase change synaptic device array

Chung Lam, H.-S. Philip Wong, Sukru Burc Eryilmaz, 2014, Front. Neurosci..

SLICE image analysis for diblock copolymer characterization and process optimization

H.-S. Philip Wong, Yang Hong, Albert Lin, 2010, Advanced Lithography.

Block copolymer directed self-assembly enables sublithographic patterning for device fabrication

H.-S. Philip Wong, He Yi, Chris Bencher, 2012, Advanced Lithography.

Robust design and experimental demonstrations of carbon nanotube digital circuits

Hai Wei, H.-S. Philip Wong, Subhasish Mitra, 2014, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference.

TRIG: hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETs

Marian Verhelst, H.-S. Philip Wong, Boris Murmann, 2018, DAC.

Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits

H.-S. Philip Wong, Jie Deng, Nishant Patil, 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Detachable nano-carbon chip with ultra low power

H.-S. Philip Wong, Xiangyu Chen, Shinobu Fujita, 2010, Design Automation Conference.

Design considerations of synaptic device for neuromorphic computing

Shimeng Yu, H.-S. Philip Wong, Duygu Kuzum, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Carbon Nanotube Transistor Circuits - Models and Tools for Design and Performance Optimization

H.-S. Philip Wong, Jie Deng, Gordon C. Wan, 2006, IEEE/ACM International Conference on Computer-Aided Design.

A 1.52 pJ/Spike Reconfigurable Multimodal Integrate-and-Fire Neuron Array Transceiver

Gert Cauwenberghs, H.-S. Philip Wong, Weier Wan, 2020, ICONS.

Video analytics using beyond CMOS devices

Narayanan Vijaykrishnan, Gert Cauwenberghs, H.-S. Philip Wong, 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Device-architecture co-design for hyperdimensional computing with 3d vertical resistive switching random access memory (3D VRRAM)

H.-S. Philip Wong, Subhasish Mitra, Haitong Li, 2017, 2017 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA).

CMOS scaling into the 21st century: 0.1 µm and beyond

Yuan Taur, H.-S. Philip Wong, David J. Frank, 1995, IBM J. Res. Dev..

Phase Change Memory: Scaling and applications

H.-S. Philip Wong, Jiale Liang, Duygu Kuzum, 2012, Proceedings of the IEEE 2012 Custom Integrated Circuits Conference.

Hyperdimensional computing with 3D VRRAM in-memory kernels: Device-architecture co-design for energy-efficient, error-resilient language recognition

Jan M. Rabaey, H.-S. Philip Wong, Mohamed M. Sabry, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Density driven placement of sub-DSA resolution assistant features (SDRAFs)

H.-S. Philip Wong, Martin D. F. Wong, Daifeng Guo, 2017, Advanced Lithography.

Energy-Efficient Abundant-Data Computing: The N3XT 1,000x

Kunle Olukotun, Franz Franchetti, Jan M. Rabaey, 2015, Computer.

Low Power Nanoscale Switching of VO2using Carbon Nanotube Heaters

Eric Pop, Miguel Munoz-Rojo, Connor McClellan, 2018, 2018 76th Device Research Conference (DRC).

In-memory computing with resistive switching devices

H.-S. Philip Wong, Daniele Ielmini, D. Ielmini, 2018, Nature Electronics.

Digital Imaging

Albert J. P. Theuwissen, H.-S. Philip Wong, Cynthia Yin, 1998, IEEE Micro.

On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network Accelerators

H.-S. Philip Wong, Paul N. Whatmough, Mudit Bhargava, 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

Nanoelectromechanical (NEM) relays integrated with CMOS SRAM for improved stability and low leakage

H.-S. Philip Wong, Subhasish Mitra, Roger T. Howe, 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

Device and circuit optimization of RRAM for neuromorphic computing

H.-S. Philip Wong, Wenqiang Zhang, Dong Wu, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Performance benchmarks for Si, III–V, TFET, and carbon nanotube FET - re-thinking the technology assessment methodology for complementary logic applications

H.-S. Philip Wong, Lan Wei, Saeroonter Oh, 2010, 2010 International Electron Devices Meeting.

Rapid exploration of processing and design guidelines to overcome carbon nanotube variations

Hai Wei, H.-S. Philip Wong, Subhasish Mitra, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

A 3D Multi-Aperture Image Sensor Architecture

H.-S. Philip Wong, Abbas El Gamal, Keith Fife, 2006, IEEE Custom Integrated Circuits Conference 2006.

Layout optimization and template pattern verification for directed self-assembly (DSA)

H.-S. Philip Wong, Zigang Xiao, He Yi, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Resistive RAM-Centric Computing: Design and Modeling Methodology

H.-S. Philip Wong, Subhasish Mitra, Haitong Li, 2017, IEEE Transactions on Circuits and Systems I: Regular Papers.

Device and Technology Challenges for Nanoscale CMOS

H.-S. Philip Wong, H. Wong, 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

Carbon nanotube circuits: Living with imperfections and variations

H.-S. Philip Wong, Nishant Patil, Subhasish Mitra, 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

Interconnect scaling into the sub-10nm regime

H.-S. Philip Wong, Xiangyu Chen, Jiale Liang, 2012, SLIP '12.

Training a Probabilistic Graphical Model With Resistive Switching Electronic Synapses

Chung Lam, Gert Cauwenberghs, H.-S. Philip Wong, 2016, IEEE Transactions on Electron Devices.

32-bit Processor core at 5-nm technology: Analysis of transistor and interconnect impact on VLSI system performance

Saurabh Sinha, H.-S. Philip Wong, Brian Cline, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Design strategy of small topographical guiding templates for sub-15nm integrated circuits contact hole patterns using block copolymer directed self assembly

H.-S. Philip Wong, He Yi, Richard Tiberio, 2013, Advanced Lithography.

Recent progress of phase change memory (PCM) and resistive switching random access memory (RRAM)

Shimeng Yu, H.-S. Philip Wong, Byoungil Lee, 2010, 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology.

Diblock copolymer directed self-assembly for CMOS device fabrication

H.-S. Philip Wong, Li-Wen Chang, 2006, SPIE Advanced Lithography.

Contact pitch and location prediction for Directed Self-Assembly template verification

Yuelin Du, H.-S. Philip Wong, Zigang Xiao, 2015, The 20th Asia and South Pacific Design Automation Conference.

A Multi-Aperture Image Sensor With 0.7 $\mu{\hbox{m}}$ Pixels in 0.11 $\mu{\hbox{m}}$ CMOS Technology

H.-S. Philip Wong, Abbas El Gamal, Keith Fife, 2008, IEEE Journal of Solid-State Circuits.

Transforming nanodevices to next generation nanosystems

H.-S. Philip Wong, Subhasish Mitra, Gage Hills, 2016, 2016 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS).

Carbon Nanotube Robust Digital VLSI

Hai Wei, H.-S. Philip Wong, Lan Wei, 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Recent Progress of Phase Change Memory (PCM) and Resistive Switching Random Access Memory (RRAM)

Shimeng Yu, H.-S. Philip Wong, Byoungil Lee, 2011, 2011 3rd IEEE International Memory Workshop (IMW).

System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits

Giovanni De Micheli, H.-S. Philip Wong, Pierre-Emmanuel Gaillardon, 2014, JETC.

Beyond the conventional transistor

H.-S. Philip Wong, H. Wong, 2002, IBM J. Res. Dev..

Computational simulation of block copolymer directed self-assembly in small topographical guiding templates

H.-S. Philip Wong, He Yi, Azat Latypov, 2013, Advanced Lithography.

Electrons in solids: a basic introduction

H.-S. Philip Wong, Deji Akinwande, 2010 .

Carbon nanotube correlation: Promising opportunity for CNFET circuit yield enhancement

Giovanni De Micheli, H.-S. Philip Wong, Nishant Patil, 2010, Design Automation Conference.

Efficient FPGAs using nanoelectromechanical relays

H.-S. Philip Wong, Nishant Patil, Subhasish Mitra, 2010, FPGA '10.

Hyperdimensional Computing Exploiting Carbon Nanotube FETs, Resistive RAM, and Their Monolithic 3D Integration

Jan M. Rabaey, H.-S. Philip Wong, Abbas Rahimi, 2018, IEEE Journal of Solid-State Circuits.

Effect of Wordline/Bitline Scaling on the Performance, Energy Consumption, and Reliability of Cross-Point Memory Array

H.-S. Philip Wong, S. Simon Wong, Jiale Liang, 2013, JETC.

Hyperdimensional Computing Nanosystem pdf

Jan M. Rabaey, H.-S. Philip Wong, Abbas Rahimi, 2018, ArXiv.

Experimental demonstration of a fully digital capacitive sensor interface built entirely using carbon-nanotube FETs

Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra, 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

NANOELECTRONICS – OPPORTUNITIES AND CHALLENGES

H.-S. Philip Wong, 2006 .

Modeling and analysis of III–V logic FETs for devices and circuits: Sub-22nm technology III–V SRAM cell design

H.-S. Philip Wong, S. Simon Wong, Jeongha Park, 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).

Combinational Logic Design Using Six-Terminal NEM Relays

H.-S. Philip Wong, Farzan Fallah, John Watkins, 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Technology Projection Using Simple Compact Models

H.-S. Philip Wong, Jie Deng, Lan Wei, 2009, 2009 International Conference on Simulation of Semiconductor Processes and Devices.

Stanford University Resistive-Switching Random Access Memory (RRAM) Verilog-A Model

H.-S. Philip Wong, Zizhen Jiang, Zizhen Jiang, 2014 .

Nanotechnology-inspired Information Processing Systems of the Future pdf

Klara Nahrstedt, H.-S. Philip Wong, Naresh Shanbhag, 2020, ArXiv.

Nano-Electro-Mechanical (NEM) relays and their application to FPGA routing

H.-S. Philip Wong, Subhasish Mitra, Chen Chen, 2012, 17th Asia and South Pacific Design Automation Conference.

Advanced cmos devices: Part II - exploratory devices and approaches

H.-S. Philip Wong, 2005 .

Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI

Ching-Te Chuang, H.-S. Philip Wong, Keunwoo Kim, 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).

Nano-engineered architectures for ultra-low power wireless body sensor nodes

H.-S. Philip Wong, David Atienza, Subhasish Mitra, 2016, 2016 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

Training and Inference in Hopfield Network Using 10 × 10 Phase Change Synaptic Array

H.-S. Philip Wong, Sukru Burc Eryilmaz, 2017 .

Energy efficient programming of nanoelectronic synaptic devices for large-scale implementation of associative and temporal sequence learning

H.-S. Philip Wong, Duygu Kuzum, Rakesh G. D. Jeyasingh, 2011, 2011 International Electron Devices Meeting.

Phase Change Memory A comprehensive and thorough review of PCM technologies, including a discussion of material and device issues, is provided in this paper.

H.-S. Philip Wong, Bipin Rajendran, Mehdi Asheghi, 2010 .

Physical Layout Design of Directed Self-Assembly Guiding Alphabet for IC Contact Hole/via Patterning

H.-S. Philip Wong, He Yi, Kye Okabe, 2015, ISPD.

Opportunities for Analog Coding in Emerging Memory Systems pdf

Chung Lam, H.-S. Philip Wong, Bruno A. Olshausen, 2017, ArXiv.

Nagarajan Raghavan, Jordi Suñé, H.-S. Philip Wong, 2018, Advanced Electronic Materials.

Design strategy for layout of Sub-Resolution Directed Self-Assembly Assist Features (SDRAFs)

H.-S. Philip Wong, Julien Ryckaert, Jan Doise, 2016 .

Fabrication and characterization of emerging nanoscale memory

Yuan Zhang, H.-S. Philip Wong, Byoungil Lee, 2009, 2009 IEEE International Symposium on Circuits and Systems.

CMOS process compatible directed block copolymer self-assembly for 20nm contact holes and beyond

H.-S. Philip Wong, Li-Wen Chang, Xin-Yu Bao, 2010, Advanced Lithography.

Special session paper 3D nanosystems enable embedded abundant-data computing

H.-S. Philip Wong, Christos Kozyrakis, Mingyu Gao, 2017, 2017 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

14.3 A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques

H.-S. Philip Wong, Edith Beigné, Pascal Vivet, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

TPAD: Hardware Trojan Prevention and Detection for Trusted Integrated Circuits

H.-S. Philip Wong, Subhasish Mitra, S. Simon Wong, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Brain-inspired computing exploiting carbon nanotube FETs and resistive RAM: Hyperdimensional computing case study

Jan M. Rabaey, H.-S. Philip Wong, Abbas Rahimi, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

Energy-Efficient Phase Change Memory Programming by Nanosecond Pulses

Eric Pop, Eilam Yalon, H.-S. Philip Wong, 2018, 2018 76th Device Research Conference (DRC).

Invited) Graphene Plane Electrode for Low Power 3D Resistive Random Access Memory

H.-S. Philip Wong, Hong-Yu Chen, Joon Sohn, 2016 .

Sensor-to-Digital Interface Built Entirely With Carbon Nanotube FETs

Hai Wei, Georges G. E. Gielen, H.-S. Philip Wong, 2014, IEEE Journal of Solid-State Circuits.

Selector Requirements for Tera-Bit Ultra-High-Density 3D Vertical RRAM

Dongjin Lee, H.-S. Philip Wong, Shosuke Fujii, 2018, 2018 IEEE Symposium on VLSI Technology.

Synaptic Devices Based on Phase-Change Memory

H.-S. Philip Wong, Yuhan Shi, Duygu Kuzum, 2017 .

Advanced CMOS devices: Part I conventional devices and technology options

H.-S. Philip Wong, 2005 .

Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits

H.-S. Philip Wong, Jie Deng, Nishant Patil, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Convergence Platforms: Foundational Science and Technology Tools

H.-S. Philip Wong, Mark Lundstrom, M. Lundstrom, 2013 .

Beyond-Silicon Devices: Considerations for Circuits and Architectures

H.-S. Philip Wong, Subhasish Mitra, Gage Hills, 2018, Beyond-CMOS Technologies for Next Generation Computer Design.

Ternary content-addressable memory with MoS2 transistors for massively parallel data search

Eric Pop, Kirby K. H. Smithe, H.-S. Philip Wong, 2019, Nature Electronics.

Device and system level design considerations for analog-non-volatile-memory based neuromorphic architectures

Shimeng Yu, H.-S. Philip Wong, Sukru Burc Eryilmaz, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

The End of the Road for 2D Scaling of Silicon CMOS and the Future of Device Technology

H.-S. Philip Wong, 2018, 2018 76th Device Research Conference (DRC).

Scaling and operation characteristics of HfOx based vertical RRAM for 3D cross-point architecture

Shimeng Yu, Bing Chen, H.-S. Philip Wong, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Face classification using electronic synapses

H.-S. Philip Wong, Luping Shi, Wenqiang Zhang, 2017, Nature Communications.

Sacha: The stanford carbon nanotube controlled handshaking robot

Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra, 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

Phase Change Memory

H.-S. Philip Wong, Simone Raoux, Mehdi Asheghi, 2010, Proceedings of the IEEE.

Stochastic learning in oxide binary synaptic device for neuromorphic computing

Shimeng Yu, H.-S. Philip Wong, Zheng Fang, 2013, Front. Neurosci..

Directed Self-Assembly (DSA) Template Pattern Verification

Yuelin Du, H.-S. Philip Wong, Zigang Xiao, 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

Time-Based Sensor Interface Circuits in CMOS and Carbon Nanotube Technologies

Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra, 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

DSA-aware detailed routing for via layer optimization

Yuelin Du, H.-S. Philip Wong, Zigang Xiao, 2014, Advanced Lithography.

Carbon nanotube computer

H.-S. Philip Wong, Subhasish Mitra, Gage Hills, 2013, Nature.

Exploration of Device Design Space to Meet Circuit Speed Targeting 22nm and Beyond

Frederic Boeuf, H.-S. Philip Wong, Dimitri A. Antoniadis, 2009 .

A Density Metric for Semiconductor Technology [Point of View]

H.-S. Philip Wong, Jeffrey Bokor, James D. Plummer, 2020, Proc. IEEE.

Block copolymer directed self-assembly (DSA) aware contact layer optimization for 10 nm 1D standard cell library

Yuelin Du, H.-S. Philip Wong, He Yi, 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Electrothermal Modeling and Design Strategies for Multibit Phase Change Memory

H.-S. Philip Wong, Jaeho Lee, Mehdi Asheghi, 2012 .

Phase-Change Memory—Towards a Storage-Class Memory

H.-S. Philip Wong, Scott W. Fong, Christopher M. Neumann, 2017, IEEE Transactions on Electron Devices.

Neuromorphic architectures with electronic synapses

Gert Cauwenberghs, H.-S. Philip Wong, Weier Wan, 2016, 2016 17th International Symposium on Quality Electronic Design (ISQED).

In quest of the next information processing substrate

Eric Pop, H.-S. Philip Wong, Michael T. Niemier, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

Density-Balancing Mask Assignment for Via Patterning with Directed Self-Assembly

H.-S. Philip Wong, Martin D. F. Wong, Daifeng Guo, 2016 .

Characterization and Design of Logic Circuits in the Presence of Carbon Nanotube Density Variations

H.-S. Philip Wong, Nishant Patil, Subhasish Mitra, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

Design strategy for integrating DSA via patterning in sub-7 nm interconnects

Geert Vandenberghe, H.-S. Philip Wong, Wim Dehaene, 2016, SPIE Advanced Lithography.

Experimental demonstration of array-level learning with phase change synaptic devices

Chung Lam, H.-S. Philip Wong, Sukru Burc Eryilmaz, 2013, 2013 IEEE International Electron Devices Meeting.

Intel LVS logic as a combinational logic paradigm in CNT technology

Xuan Zeng, Zhen Cao, H.-S. Philip Wong, 2010, 2010 IEEE/ACM International Symposium on Nanoscale Architectures.

2D analytical model for the study of NEM relay device scaling

H.-S. Philip Wong, Xiaoying Shen, Roger T. Howe, 2011, 2011 International Conference on Simulation of Semiconductor Processes and Devices.

Design method and algorithms for directed self-assembly aware via layout decomposition in sub-7 nm circuits

Geert Vandenberghe, H.-S. Philip Wong, Wim Dehaene, 2016 .

Circuit-aware device reliability criteria methodology

H.-S. Philip Wong, Lan Wei, Anthony S. Oates, 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

Templated DSA vias in sub-7 nm circuits: Design strategy and DSA-aware via decomposition

Geert Vandenberghe, H.-S. Philip Wong, Wim Dehaene, 2016 .

Rapid Co-Optimization of Processing and Circuit Design to Overcome Carbon Nanotube Variations

Hai Wei, H.-S. Philip Wong, Subhasish Mitra, 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A systems approach to computing in beyond CMOS fabrics

Jan M. Rabaey, Naresh R. Shanbhag, Eric Pop, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

A 3MPixel Multi-Aperture Image Sensor with 0.7μm Pixels in 0.11μm CMOS

H.-S. Philip Wong, Abbas El Gamal, Keith Fife, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

Impact of III–V and Ge Devices on Circuit Performance

H.-S. Philip Wong, Soyoung Kim, S. Simon Wong, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Design guidelines for 3D RRAM cross-point architecture

Shimeng Yu, Bing Chen, H.-S. Philip Wong, 2014, 2014 IEEE International Symposium on Circuits and Systems (ISCAS).

Coming Up N3XT, After 2D Scaling of Si CMOS

H.-S. Philip Wong, Weier Wan, Subhasish Mitra, 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

Carbon nanotube imperfection-immune digital VLSI: Frequently asked questions updated

Hai Wei, H.-S. Philip Wong, Lan Wei, 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

Diblock copolymer directed self-assembly for CMOS device fabrication

H.-S. Philip Wong, Li-Wen Chang, Marissa A. Caldwell, 2008, SPIE Advanced Lithography.

Carbon nanotube circuits: Opportunities and challenges

Hai Wei, H.-S. Philip Wong, Subhasish Mitra, 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique

H.-S. Philip Wong, Subhasish Mitra, Chen Chen, 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Joint Source-Channel Coding with Neural Networks for Analog Data Compression and Storage

H.-S. Philip Wong, Bruno A. Olshausen, Jesse Engel, 2018, 2018 Data Compression Conference.

CMOS technology roadmap projection including parasitic effects

Frederic Boeuf, Thomas Skotnicki, H.-S. Philip Wong, 2009, 2009 International Symposium on VLSI Technology, Systems, and Applications.

Challenges and opportunities toward online training acceleration using RRAM-based hardware neural network

H.-S. Philip Wong, Chih-Cheng Chang, Tuo-Hung Hou, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Monolithic 3D integration: A path from concept to reality

Hai Wei, H.-S. Philip Wong, Mohamed M. Sabry, 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

Resistive RAM With Multiple Bits Per Cell: Array-Level Demonstration of 3 Bits Per Cell

H.-S. Philip Wong, Edith Beigne, Elisa Vianello, 2019, IEEE Transactions on Electron Devices.

Time-based sensor interface circuits in carbon nanotube technology

Georges G. E. Gielen, H.-S. Philip Wong, Subhasish Mitra, 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

Beyond the conventional transistor

H.-S. Philip Wong, 2002, IBM J. Res. Dev..

Modeling and design optimization of ReRAM

H.-S. Philip Wong, Peng Huang, Jinfeng Kang, 2015, The 20th Asia and South Pacific Design Automation Conference.

DSA template optimization for contact layer in 1D standard cell design

Yuelin Du, H.-S. Philip Wong, Zigang Xiao, 2014, Advanced Lithography.

Digital VLSI logic technology using Carbon Nanotube FETs: Frequently Asked Questions

H.-S. Philip Wong, Nishant Patil, Subhasish Mitra, 2009, 2009 46th ACM/IEEE Design Automation Conference.

Contact-hole patterning for random logic circuits using block copolymer directed self-assembly

H.-S. Philip Wong, Jie Zhang, He Yi, 2012, Advanced Lithography.

Device and circuit interactive design and optimization beyond the conventional scaling era

H.-S. Philip Wong, Lan Wei, Jieying Luo, 2010, 2010 International Electron Devices Meeting.

Scanning the issue

Mohamed-Slim Alouini, Tareq Y. Al-Naffouri, Elias Yaacoub, 2019, IEEE Trans. Autom. Control..

Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections

H.-S. Philip Wong, Jie Deng, Nishant Patil, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

3D nanosystems enable embedded abundant-data computing: special session paper

Christoforos E. Kozyrakis, H.-S. Philip Wong, Mingyu Gao, 2017, CODES+ISSS.

Ultra-low power Al2O3-based RRAM with 1μA reset current

H.-S. Philip Wong, Byoungil Lee, H. Wong, 2010, Proceedings of 2010 International Symposium on VLSI Technology, System and Application.

First demonstration of phase change memory device using solution processed GeTe nanoparticles

H.-S. Philip Wong, Delia J. Milliron, Marissa A. Caldwell, 2011, 2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

2D molybdenum disulfide (MoS2) transistors driving RRAMs with 1T1R configuration

Eric Pop, Kirby K. H. Smithe, H.-S. Philip Wong, 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

Performance Estimation and Benchmarking for Carbon Nanotube FETs and Nanodiode Arrays

Gary S. Ditlow, H.-S. Philip Wong, Paul M. Solomon, 2003 .

Experimental Demonstration and Characterization of on-chip high speed graphene interconnects

Jing Kong, H.-S. Philip Wong, Shinobu Fujita, 2010 .

Monolithic three-dimensional integrated circuits using carbon nanotube FETs and interconnects

Hai Wei, H.-S. Philip Wong, Subhasish Mitra, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Thickness and stoichiometry dependence of the thermal conductivity of GeSbTe films

Eric Pop, H.-S. Philip Wong, Kenneth E. Goodson, 2007 .

Microsecond transient thermal behavior of HfOx-based resistive random access memory using a micro thermal stage (MTS)

H.-S. Philip Wong, Yoshio Nishi, Hong-Yu Chen, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Understanding the switching mechanism of interfacial phase change memory

Eric Pop, Eilam Yalon, H.-S. Philip Wong, 2019, Journal of Applied Physics.

High-speed graphene interconnects monolithically integrated with CMOS ring oscillators operating at 1.3GHz

Jing Kong, H.-S. Philip Wong, Shinobu Fujita, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Beyond the Conventional MOSFET

H.-S. Philip Wong, H. Wong, 2001 .

Carbon nanotube electronics - Materials, devices, circuits, design, modeling, and performance projection

Hai Wei, Jie Zhang, H.-S. Philip Wong, 2011, 2011 International Electron Devices Meeting.

First Demonstration of AC Gain From a Single-walled Carbon Nanotube Common-Source Amplifier

H.-S. Philip Wong, Jie Deng, Islamshah Amlani, 2006, 2006 International Electron Devices Meeting.

Electronic synapses made of layered two-dimensional materials

Eric Pop, H.-S. Philip Wong, Mario Lanza, 2018, Nature Electronics.

Carbon Nanotube and Graphene Device Physics: Carbon nanotubes

H.-S. Philip Wong, Deji Akinwande, H. Wong, 2010 .

Low-voltage high-performance flexible digital and analog circuits based on ultrahigh-purity semiconducting carbon nanotubes

Kwang-Ting Cheng, H.-S. Philip Wong, Tsung-Ching Huang, 2019, Nature Communications.

AC conductance measurement and analysis of the conduction processes in HfOx based resistive switching memory

Shimeng Yu, H.-S. Philip Wong, Rakesh Jeyasingh, 2011 .

BEOL compatible graphene/Cu with improved electromigration lifetime for future interconnects

Tao Wang, H.-S. Philip Wong, Alex Yoon, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

Air-stable technique for fabricating n-type carbon nanotube FETs

Hai Wei, H.-S. Philip Wong, Subhasish Mitra, 2011, 2011 International Electron Devices Meeting.

In situ transmission electron microscopy observation of nanostructural changes in phase-change memory.

H.-S. Philip Wong, Stefan Meister, SangBum Kim, 2011, ACS nano.

Impact of fixed charge on metal-insulator-semiconductor barrier height reduction

H.-S. Philip Wong, Krishna C. Saraswat, Aneesh Nainani, 2011 .

Top-gated FETs/inverters with diblock copolymer self-assembled 20 nm contact holes

H.-S. Philip Wong, Li-Wen Chang, Clement H. Wann, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

SRAM, NAND, DRAM contact hole patterning using block copolymer directed self-assembly guided by small topographical templates

H.-S. Philip Wong, Huixiong Dai, Yongmei Chen, 2011, 2011 International Electron Devices Meeting.

Metal/III-V Schottky barrier height tuning for the design of nonalloyed III-V field-effect transistor source/drain contacts

H.-S. Philip Wong, Krishna C. Saraswat, Jenny Hu, 2010 .

Understanding Energy Efficiency Benefits of Carbon Nanotube Field-Effect Transistors for Digital VLSI

Francky Catthoor, H.-S. Philip Wong, Iuliana Radu, 2018, IEEE Transactions on Nanotechnology.

Dual-Layer Dielectric Stack for Thermally-Isolated Low-Power Phase-Change Memory

H.-S. Philip Wong, Scott W. Fong, Chris M. Neumann, 2017, 2017 IEEE International Memory Workshop (IMW).

SiGe-on-insulator prepared by wafer bonding and layer transfer for high-performance field-effect transistors

H.-S. Philip Wong, Steven J. Koester, Jack O. Chu, 2001 .

Dual-Layer Dielectric Stack for Thermally Isolated Low-Energy Phase-Change Memory

Eric Pop, Eilam Yalon, H.-S. Philip Wong, 2017, IEEE Transactions on Electron Devices.

High-speed graphene interconnects monolithically integrated with CMOS ring oscillators operating at 1 . 3 GHz Citation

Jing Kong, H.-S. Philip Wong, Shinobu Fujita, 2009 .

1D thickness scaling study of phase change material (Ge2Sb2Te5) using a pseudo 3-terminal device

H.-S. Philip Wong, Joo-Tae Moon, Yuan Zhang, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

On the Variability of HfOx RRAM: From Numerical Simulation to Compact Modeling

Shimeng Yu, H.-S. Philip Wong, Ximeng Guan, 2012 .

Removable and Recyclable Conjugated Polymers for Highly Selective and High-Yield Dispersion and Release of Low-Cost Carbon Nanotubes.

H.-S. Philip Wong, Xiyuan Chen, Zhenan Bao, 2016, Journal of the American Chemical Society.

Crystallization properties and their drift dependence in phase-change memory studied with a micro-thermal stage

H.-S. Philip Wong, Byoungil Lee, Kenneth E. Goodson, 2011 .

Hysteresis-Free Carbon Nanotube Field-Effect Transistors.

H.-S. Philip Wong, Subhasish Mitra, Gage Hills, 2017, ACS nano.

A Physics-Based Compact Model for CBRAM Retention Behaviors Based on Atom Transport Dynamics and Percolation Theory

H.-S. Philip Wong, Jinfeng Kang, Lifeng Liu, 2019, IEEE Electron Device Letters.

Carbon Nanotube Device Modeling and Circuit Simulation

H.-S. Philip Wong, Jie Deng, Albert Lin, 2009 .

Ultrafast Accelerated Retention Test Methodology for RRAM Using Micro Thermal Stage

H.-S. Philip Wong, Yoshio Nishi, Hong-Yu Chen, 2017, IEEE Electron Device Letters.

Characterization of low-frequency noise in the resistive switching of transition metal oxide HfO 2

Shimeng Yu, H.-S. Philip Wong, Rakesh Jeyasingh, 2012 .

Increasing the semiconducting fraction in ensembles of single-walled carbon nanotubes

H.-S. Philip Wong, Albert Lin, Hong-Yu Chen, 2012 .

One-Dimensional Thickness Scaling Study of Phase Change Material ({Ge}_{2}{Sb}_{2}{Te}_{5}) Using a Pseudo 3-Terminal Device

H.-S. Philip Wong, In-Gyu Baek, Seok-Woo Nam, 2011 .

Transient dynamics of NbOx threshold switches explained by Poole-Frenkel based thermal feedback mechanism

H.-S. Philip Wong, Yoshio Nishi, Suhas Kumar, 2018 .

Size limitation of cross-point memory array and its dependence on data storage pattern and device parameters

H.-S. Philip Wong, Jiale Liang, H. Wong, 2010, 2010 IEEE International Interconnect Technology Conference.

Synthesis and Size-Dependent Crystallization of Colloidal Germanium Telluride

H.-S. Philip Wong, Simone Raoux, Delia J. Milliron, 2010 .

Carrier density and quantum capacitance for semiconducting carbon nanotubes

H.-S. Philip Wong, Deji Akinwande, Jiale Liang, 2008 .

Scaling the CBRAM Switching Layer Diameter to 30 nm Improves Cycling Endurance

H.-S. Philip Wong, Shosuke Fujii, Mario Lanza, 2018, IEEE Electron Device Letters.

Device study, chemical doping, and logic circuits based on transferred aligned single-walled carbon nanotubes

H.-S. Philip Wong, Subhasish Mitra, Albert Lin, 2008 .

Low frequency noise in phase change materials

H.-S. Philip Wong, Gerard Ghibaudo, Mireille Mouis, 2011, 2011 21st International Conference on Noise and Fluctuations.

Metal-induced dopant (boron and phosphorus) activation process in amorphous germanium for monolithic three-dimensional integration

H.-S. Philip Wong, Krishna C. Saraswat, Munehiro Tada, 2009 .

A non-iterative compact model for carbon nanotube FETs incorporating source exhaustion effects

H.-S. Philip Wong, David J. Frank, Leland Chang, 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

Phase Change Nanodots Patterning using a Self-Assembled Polymer Lithography and Crystallization Analysis

H.-S. Philip Wong, Philip M. Rice, Daniel Krebs, 2008 .

Template Patterning: Flexible Control of Block Copolymer Directed Self-Assembly using Small, Topographical Templates: Potential Lithography Solution for Integrated Circuit Contact Hole Patterning (Adv. Mater. 23/2012)

H.-S. Philip Wong, Huixiong Dai, Yongmei Chen, 2012 .

Nanometer-Scale ${\rm HfO}_{x}$ RRAM

H.-S. Philip Wong, H. Wong, Zhiping Zhang, 2013, IEEE Electron Device Letters.

Thermal disturbance and its impact on reliability of phase-change memory studied by the micro-thermal stage

H.-S. Philip Wong, Byoungil Lee, Mehdi Asheghi, 2010, 2010 IEEE International Reliability Physics Symposium.