M. E. Gómez

发表

Validation of algorithm used for location of electrodes in CT images

Juan Pablo Graffigna, R. Romo, J Bustos, 2013 .

Application Clustering Policies to Address System Fairness with Intel’s Cache Allocation Technology

Lieven Eeckhout, Vicent Selfa, Julio Sahuquillo, 2017, 2017 26th International Conference on Parallel Architectures and Compilation Techniques (PACT).

Impact of the Array Shape and Memory Bandwidth on the Execution Time of CNN Systolic Arrays

Julio Sahuquillo, Salvador Petit, Eduardo Yago, 2020, 2020 23rd Euromicro Conference on Digital System Design (DSD).

Speeding-up the fault-tolerance analysis of interconnection networks

Pedro López, María Engracia Gómez, Crispín Gómez Requena, 2015, 2015 International Conference on High Performance Computing & Simulation (HPCS).

Exploiting Network-on-Chip structural redundancy for a cooperative and scalable built-in self-test architecture

Michele Favalli, Daniele Ludovici, Alessandro Strano, 2011, 2011 Design, Automation & Test in Europe.

Effect of Hyper-Threading in Latency-Critical Multithreaded Cloud Applications and Utilization Analysis of the Major System Resources

M. E. Gómez, J. Sahuquillo, S. Petit, 2022, Future Gener. Comput. Syst..

PS-Cache: an energy-efficient cache design for chip multiprocessors

Alberto Ros, Julio Sahuquillo, María Engracia Gómez, 2013, The Journal of Supercomputing.

HoL-Blocking Avoidance Routing Algorithms in Direct Topologies

José Duato, María Engracia Gómez, Roberto Peñaranda, 2014, 2014 IEEE Intl Conf on High Performance Computing and Communications, 2014 IEEE 6th Intl Symp on Cyberspace Safety and Security, 2014 IEEE 11th Intl Conf on Embedded Software and Syst (HPCC,CSS,ICESS).

A Hardware Approach to Fairly Balance the Inter-Thread Interference in Shared Caches

Vicent Selfa, Julio Sahuquillo, Salvador Petit, 2017, IEEE Transactions on Parallel and Distributed Systems.

An Efficient Fault-Tolerant Routing Methodology for Meshes and Tori

Antonio Robles, Pedro López, José Duato, 2004, IEEE Computer Architecture Letters.

A routing methodology for achieving fault tolerance in direct networks

Antonio Robles, Pedro López, José Duato, 2006, IEEE Transactions on Computers.

A New Adaptive Fault-Tolerant Routing Methodology for Direct Networks

Antonio Robles, Pedro López, José Duato, 2004, HiPC.

An effective fault-tolerant routing methodology for direct networks

M. E. Gómez, J. Duato, P. López, 2004, International Conference on Parallel Processing, 2004. ICPP 2004..

VOQ/sub SW/: a methodology to reduce HOL blocking in InfiniBand networks

Antonio Robles, Pedro López, José Duato, 2003, Proceedings International Parallel and Distributed Processing Symposium.

An Efficient Fault-Tolerant Routing Methodology for Fat-Tree Interconnection Networks

Pedro López, José Duato, María Engracia Gómez, 2007, ISPA.

A Memory-Effective Fault-Tolerant Routing Strategy for Direct Interconnection Networks

Pedro López, José Duato, María Engracia Gómez, 2005, The 4th International Symposium on Parallel and Distributed Computing (ISPDC'05).

A memory-effective routing strategy for regular interconnection networks

Pedro López, José Duato, María Engracia Gómez, 2005, 19th IEEE International Parallel and Distributed Processing Symposium.

FIR: An efficient routing strategy for tori and meshes

Pedro López, José Duato, María Engracia Gómez, 2006, J. Parallel Distributed Comput..

Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework

Luca Benini, Pedro López, José Duato, 2008, Second ACM/IEEE International Symposium on Networks-on-Chip (nocs 2008).

Segment Switching: A New Switching Strategy for Optical HPC Networks

Julio Sahuquillo, Salvador Petit, María E. Gómez, 2021, IEEE Access.

The k-ary n-direct s-indirect family of topologies for large-scale interconnection networks

Pedro López, José Duato, María Engracia Gómez, 2016, The Journal of Supercomputing.

Towards an Efficient Fat-Tree like Topology

Pedro López, José Duato, María Engracia Gómez, 2012, Euro-Par.

A New Family of Hybrid Topologies for Large-Scale Interconnection Networks

Pedro López, José Duato, María Engracia Gómez, 2012, 2012 IEEE 11th International Symposium on Network Computing and Applications.

Assessing fat-tree topologies for regular network-on-chip design under nanoscale technology constraints

Pedro López, Daniele Ludovici, Davide Bertozzi, 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

Beyond Fat--tree: Unidirectional Load--Balanced Multistage Interconnection Network

Pedro López, José Duato, María Engracia Gómez, 2008, IEEE Computer Architecture Letters.

An efficient cache flat storage organization for multithreaded workloads for low power processors

Julio Sahuquillo, Salvador Petit, José Puche, 2020, Future Gener. Comput. Syst..

Modeling and analysis of the performance of exascale photonic networks

Maria E. Gomez, Julio Sahuquillo, Salvador Petit, 2018, Concurr. Comput. Pract. Exp..

Workload Characterization for Exascale Computing Networks

Julio Sahuquillo, Salvador Petit, María Engracia Gómez, 2018, 2018 International Conference on High Performance Computing & Simulation (HPCS).

Analysis of self-similarity in I/O workload using structural modeling

María Engracia Gómez, Vicente Santonja, M. E. Gómez, 1999, MASCOTS '99. Proceedings of the Seventh International Symposium on Modeling, Analysis and Simulation of Computer and Telecommunication Systems.

TLB-Based Temporality-Aware Classification in CMPs with Multilevel TLBs

Antonio Robles, José Duato, Alberto Ros, 2017, IEEE Transactions on Parallel and Distributed Systems.

Deterministic versus Adaptive Routing in Fat-Trees

Pedro López, José Duato, María Engracia Gómez, 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.