V. Visvanathan

发表

Reconfigurable Filter Coprocessor Architecture for DSP Applications

S. K. Nandy, S. Ramanathan, V. Visvanathan, 2000, J. VLSI Signal Process..

A CORDIC based programmable DXT processor array

V. Visvanathan, V. K. Anuradha, 1994, Proceedings of 7th International Conference on VLSI Design.

A self-biased high performance folded cascode CMOS op-amp

Pradip Mandal, V. Visvanathan, 1997, Proceedings Tenth International Conference on VLSI Design.

A systolic architecture for LMS adaptive filtering with minimal adaptation delay

S. Ramanathan, V. Visvanathan, 1996, Proceedings of 9th International Conference on VLSI Design.

Comparative analysis of approaches to hardware acceleration for sparse-matrix factorization

P. Sadayappan, V. Visvanathan, 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

A computational engine for multirate FIR digital filtering

S. K. Nandy, S. Ramanathan, V. Visvanathan, 1999, Signal Process..

A 230 MHz Half Bit Level Pipelined Multiplier using True Single Phase Clocking

Dinesh Somasekhar, V. Visvanathan, 1993, The Sixth International Conference on VLSI Design.

Automatic generation of tree multipliers using placement-driven netlists

S. K. Nandy, V. Visvanathan, Avinash K. Gautam, 1999, Proceedings 1999 IEEE International Conference on Computer Design: VLSI in Computers and Processors (Cat. No.99CB37040).

Within-Die Gate Delay Variability Measurement Using Reconfigurable Ring Oscillator

H.S. Jamadagni, V. Visvanathan, B.P. Das, 2009, IEEE Transactions on Semiconductor Manufacturing.

Circuit Simulation on Shared-Memory Multiprocessors

P. Sadayappan, V. Visvanathan, P. Sadayappan, 1988, IEEE Trans. Computers.

Parallel Direct Solution of Sparse Linear Systems

P. Sadayappan, V. Visvanathan, Kalluri Eswar, 1993 .

An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters

S. Ramanathan, V. Visvanathan, Nibedita Mohanty, 1993, The Sixth International Conference on VLSI Design.

Statistical device models from worst case files and electrical test data

V. Visvanathan, K. Singhal, V. Visvanathan, 1999 .

Low-power configurable processor array for DLMS adaptive filtering

S. Ramanathan, V. Visvanathan, 1997, Proceedings Tenth International Conference on VLSI Design.

Loop-Based and Device-Based Algorithms for Stability Analysis of Linear Analog Circuits in the Frequency Domain

V. Visvanathan, Michael Tian, Jeffrey Hantgan, 2001 .

Supernodal Sparse Cholesky Factorization on Distributed-Memory Multiprocessors

P. Sadayappan, Chua-Huang Huang, V. Visvanathan, 1993, 1993 International Conference on Parallel Processing - ICPP'93.

A modular systolic architecture for delayed least mean squares adaptive filtering

S. Ramanathan, V. Visvanathan, 1995, Proceedings of the 8th International Conference on VLSI Design.

T4: VLSI Implementation of DSP Architectures

V. Visvanathan, A. Ratan Gupta, 1996 .

CMOS op-amp sizing using a geometric programming formulation

Pradip Mandal, V. Visvanathan, V. Visvanathan, 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Design of high performance two stage CMOS cascode op-amps with stable biasing

Pradip Mandal, V. Visvanathan, 1996, Proceedings of 9th International Conference on VLSI Design.

Multifrontal Factorization of Sparse Matrices on Shared-Memory Multiprocessors

P. Sadayappan, V. Visvanathan, Kalluri Eswar, 1991, ICPP.

Striving for small-signal stability

V. Visvanathan, K. Kundert, M. Tian, 2001, IEEE Circuits and Devices Magazine.

Diagnosability of Nonlinear Circuits and Systems—Part II: Dynamical Systems

Alberto L. Sangiovanni-Vincentelli, V. Visvanathan, Richard Saeks, 1981, IEEE Transactions on Computers.

An efficient algorithm to determine the image of a parallelepiped under a linear transformation

Linda S. Milor, V. Visvanathan, 1986, SCG '86.

Application of DC transfer characteristics in the elimination of redundant vectors for transient noise characterization of static CMOS circuits

V. Visvanathan, Sreeram Chandrasekar, Gaurav Kumar Varshney, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

A comprehensive methodology for noise characterization of ASIC cell libraries

V. Visvanathan, Sreeram Chandrasekar, Gaurav Kumar Varshney, 2005, Sixth international symposium on quality electronic design (isqed'05).

Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks

Bharadwaj S. Amrutur, V. Visvanathan, Janakiraman Viraraghavan, 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A new approach for CMOS op-amp synthesis

Pradip Mandal, V. Visvanathan, 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

A Methodology for Generating Application Specific Tree Multipliers

S. Ramanathan, V. Visvanathan, Nibedita Mohanty, 1993, The Sixth International Conference on VLSI Design.

Detection of catastrophic faults in analog integrated circuits

Linda S. Milor, V. Visvanathan, V. Visvanathan, 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Within-die gate delay variability measurement using re-configurable ring oscillator

Bharadwaj S. Amrutur, H. S. Jamadagni, V. Visvanathan, 2008, 2008 IEEE Custom Integrated Circuits Conference.

Supply and Body-Bias Voltage Assignment Based Technique for Power and Temperature Control on a Chip at Iso-Performance Conditions

V. Kamakoti, Milan Patnaik, V. R. Devanathan, 2013, J. Low Power Electron..

The center design optimization system

Sani R. Nassif, Colin C. McAndrew, Kishore Singhal, 1989, AT&T Technical Journal.

Architectural Synthesis of Computational Engines for Subband Adaptive Filtering

S. K. Nandy, S. Ramanathan, V. Visvanathan, 1999, J. VLSI Signal Process..

NPCPL : Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs

S. K. Nandy, V. Visvanathan, Debabrata Ghosh, 1993, The Sixth International Conference on VLSI Design.

Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications

V. Kamakoti, V. R. Devanathan, V. Visvanathan, 2015, J. Low Power Electron..

Parallelization and performance evaluation of circuit simulation on a shared-memory multiprocessor

P. Sadayappan, V. Visvanathan, P. Sadayappan, 1988, ICS '88.

A Framework for Scheduling Multi-rate Circuit Simulation

V. Visvanathan, Antony P.-C. Ng, 1989, 26th ACM/IEEE Design Automation Conference.

Synthesis of ASIPs for DSP algorithms

S. K. Nandy, S. Ramanathan, V. Visvanathan, 1999, Integr..

Application of alpha power law models to PLL design methodology

H. S. Jamadagni, V. Visvanathan, R. S. Krishnan, 2005, 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design.

A Computational Approach for the Diagnosability of Dynamical Circuits

Alberto L. Sangiovanni-Vincentelli, V. Visvanathan, 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

High speed digital filtering on SRAM-based FPGAs

S. K. Nandy, V. Visvanathan, S. K. Ghoshal, 1994, Proceedings of 7th International Conference on VLSI Design.

Macromodeling of the A.C. characteristics of CMOS Op-amps

Pradip Mandal, V. Visvanathan, 1993, ICCAD.

Efficient sparse matrix factorization for circuit simulation on vector supercomputers

P. Sadayappan, V. Visvanathan, 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs

V. Kamakoti, V. R. Devanathan, V. Visvanathan, 2014, 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems.

A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array

S. K. Nandy, Ranjani Narayan, P. Sadayappan, 1993, 1993 International Conference on Parallel Processing - ICPP'93.

VLSI Implementation of DSP Architectures

V. Visvanathan, A. Ratan Gupta, 1996, VLSI Design.

Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs

V. Kamakoti, V. R. Devanathan, V. Visvanathan, 2012, J. Low Power Electron..

A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase Clocking

Dinesh Somasekhar, V. Visvanathan, 1993, VLSI Design.

Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks

Bharadwaj S. Amrutur, V. Visvanathan, Janakiraman Viraraghavan, 2008, J. Low Power Electron..

Synthesis of configurable architectures for DSP algorithms

S. K. Nandy, S. Ramanathan, V. Visvanathan, 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

Testing of Analog Integrated Circuits

V. Visvanathan, 1991 .

Diagnosability of Nonlinear Circuits and Systems—Part I: The dc Case

Alberto L. Sangiovanni-Vincentelli, V. Visvanathan, 1981, IEEE Transactions on Computers.

Sequentially linear fault diagnosis: Part II-The design of diagnosable systems

Ruey-Wen Liu, V. Visvanathan, 1979 .

Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay1

S. Ramanathan, V. Visvanathan, 1999, Integr..

Efficient Sparse Matrix Factorization for Circuit Simulation on Vector Supercomputers

P. Sadayappan, V. Visvanathan, P. Sadayappan, 1989, 26th ACM/IEEE Design Automation Conference.

Architectural Synthesis of Low-Power Computational Engines for LMS Adaptive Filtering

S. K. Nandy, S. Ramanathan, V. Visvanathan, 1998 .

Self-biasing of folded cascode CMOS op-amps

Pradip Mandal, V. Visvanathan, V. Visvanathan, 2000 .