Kwang-Il Park

发表

A 21 nm High Performance 64 Gb MLC NAND Flash Memory With 400 MB/s Asynchronous Toggle DDR Interface

Young-Hyun Jun, Jinho Ryu, Changhyun Cho, 2012, IEEE Journal of Solid-State Circuits.

A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration

Yun-Sik Park, Chang-Kyo Lee, Jung-Bae Lee, 2019, 2019 Symposium on VLSI Circuits.

An Enhanced Built-off-Test Transceiver with Wide-range, Self-calibration Engine for 3.2 Gb/s/pin DDR4 SDRAM

Dong-Hun Lee, Kiho Kim, Yong-Ho Cho, 2018, 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A crosstalk-and-ISI equalizing receiver in 2-drop single-ended SSTL memory channel

Young-Hyun Jun, Jae-Yoon Sim, Hong-June Park, 2010, IEEE Custom Integrated Circuits Conference 2010.

A Study on the Optical Properties of Diffuse Reflector Surface Structure

Jong-Tae Kim, Young Moon Yu, Kwang-Il Park, 2017 .

Semiconductor memory device and associated access method

Hye-Ran Kim, Kwang-Il Park, Dae-Hyun Hwaseong Kim, 2009 .

(A) fast simulation methodology in VLSI circuits = VLSI 회로에서의 고속 시뮬레이션 방법론에 관한 연구

박광일, Kwang-Il Park, 1999 .

A bandwidth-efficient implementation of mesh with multiple broadcasting

Kyu Ho Park, Bong Wan Kim, Kwang-Il Park, 1999, Proceedings of the 1999 International Conference on Parallel Processing.

A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme

Young-Hyun Jun, Lee-Sup Kim, Kinam Kim, 2008, 2008 IEEE Custom Integrated Circuits Conference.

23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

Sukhyun Lim, Jin-Hun Jang, Dukha Park, 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).

A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process

Jae-Joon Song, Kyung-Soo Kim, Jongmin Kim, 2018, 2018 IEEE Symposium on VLSI Circuits.

23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devices

Hyun-Soo Park, Hyuk-Jun Kwon, Jong-Ho Lee, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A Sub-1.0V 20nm 5Gb/s/pin post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and adaptive calibration scheme for mobile application

Jung-Hwan Choi, Min-Ho Park, Kwang-Il Park, 2013, 2013 Symposium on VLSI Circuits.

Dual-loop 2-step ZQ calibration for dedicated power supply voltage in LPDDR4 SDRAM

Junha Lee, Jung-Hwan Choi, Joon-Young Park, 2017, 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A Skew-tolerant Wave-Pipelined Router on FPGA

Kyu Ho Park, Kwang-Il Park, Jong-Kwon Choi, 1999 .

Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation

Young-Hyun Jun, Jae-Hyuk Oh, Bai-Sun Kong, 2009, IEEE Transactions on Circuits and Systems II: Express Briefs.

A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces

Young-Hyun Jun, Lee-Sup Kim, Kinam Kim, 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 60nm 6Gb/s/pin GDDR5 Graphics DRAM with Multifaceted Clocking and ISI/SSN-Reduction Techniques

Jae-Hyung Lee, Young-Hyun Jun, Dae-Hyun Kim, 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction

Jae-Hyung Lee, Young-Hyun Jun, Dong-Min Kim, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage–Frequency Scaling in LPDDR4 SDRAM

Dong-Hun Lee, Junha Lee, Jung-Hwan Choi, 2018, IEEE Journal of Solid-State Circuits.

A 0.13-$\mu$ m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN

Young-Hyun Jun, Lee-Sup Kim, Kinam Kim, 2009, IEEE Journal of Solid-State Circuits.

PVT-invariant single-to-differential data converter with minimum skew and duty-ratio distortion

Young-Hyun Jun, Jeong-Don Ihm, Bai-Sun Kong, 2008, 2008 IEEE International Symposium on Circuits and Systems.

A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM With Integrated ECC Engine for Sub-1 V DRAM Core Operation

Hyoung-Joo Kim, Jong-Ho Lee, Jun-Young Park, 2015, IEEE Journal of Solid-State Circuits.

High-Speed Low-Power Global On-Chip Interconnect Based on Delayed Symbol Transmission

Young-Hyun Jun, Kwang-Il Park, Bai-Sun Kong, 2012 .

18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution

Yong-Jun Kim, Young-Sik Kim, Ju-Hwan Kim, 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking

Hyun-Soo Park, Hyuk-Jun Kwon, Kyungbae Park, 2019, IEEE Journal of Solid-State Circuits.

A Phase-Locked Loop with Reference Clock-Based Locking Time for Above-2.0Gb/s/pin DRAM Interface

Young-Hyun Jun, Jong-Woo Kim, Nam-Seog Kim, 2007 .

A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW

Young-Hyun Jun, Dae-Hyun Kim, Young-Sik Kim, 2011, 2011 IEEE International Solid-State Circuits Conference.

23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme

Jonghyuk Kim, Hoon Lee, Young Choi, 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).

A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme

Young-Hyun Jun, Lee-Sup Kim, Kwang-Il Park, 2009, IEEE J. Solid State Circuits.

HMM and Rule-Based Hybrid Intruder Detection Approach by Synthesizing Decisions of Sensors

Kyungmin Kim, Wooju Kim, Kwang-Il Park, 2013, Int. J. Distributed Sens. Networks.

Event suppression by optimizing VHDL programs

Kyu Ho Park, Kwang-Il Park, Kwang-il Park, 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

A 40nm 7Gb/s/pin single-ended transceiver with jitter and ISI reduction techniques for high-speed DRAM interface

Young-Hyun Jun, Dong-Min Kim, Young-Sik Kim, 2010, 2010 Symposium on VLSI Circuits.

Study of the Optical System Design for Omni-Directional LED Bulb Satisfying Energy Star’s Light Bulbs Specification

Jong-Tae Kim, Young Moon Yu, Kwang-Il Park, 2017 .

The acceleration of VHDL simulation by classifying events

Kyu Ho Park, Kwang-Il Park, Heung Bum Kim, 1997, Proceedings of 1997 SCS Simulation Multiconference.

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

Hoon Shin, Young Choi, Inkyu Moon, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

A DLL with Jitter-Reduction Techniques for DRAM Interfaces

Young-Hyun Jun, Lee-Sup Kim, Soo-In Cho, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

A wormhole router with embedded broadcasting virtual bus for mesh computers

Kyu Ho Park, Bong Wan Kim, Kwang-Il Park, 2000 .

A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme

Young-Hyun Jun, Kwang-Il Park, Lee-Sup Kim, 2009, IEEE Journal of Solid-State Circuits.

A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces

Young-Hyun Jun, Lee-Sup Kim, Soo-In Cho, 2009, IEEE Journal of Solid-State Circuits.

Data processing device, system and method

Kwang-Il Park, Young-Soo Sohn, Dong-Min Kim, 2011 .

Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices

O Seongil, Jung Ho Ahn, Nam Sung Kim, 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).

Low-jitter multi-phase digital DLL with closest edge selection scheme for DDR memory interface

Kinam Kim, Young-Hyun Jun, Lee-Sup Kim, 2008 .

A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

Yong Jae Lee, Hyun-Soo Park, Hyuk-Jun Kwon, 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

A Wormhole Router with Embedded Broadcasting Virtual Bus for Mesh Computers

Kyu Ho Park, Bong Wan Kim, Kwang-Il Park, 2000, Parallel Process. Lett..

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

Woo-Jin Lee, Young-Hyun Jun, Jeong-Don Ihm, 2008, IEEE Journal of Solid-State Circuits.

Cancelation of a crosstalk induced noise in a DDR memory interface

Young-Hyun Jun, Lee-Sup Kim, Kinam Kim, 2008, 2008 International SoC Design Conference.

Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM

Sung Kyu Lim, Yarui Peng, Bon Woong Ku, 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction

Jae-Hyung Lee, Young-Hyun Jun, Dong-Min Kim, 2011, IEEE Journal of Solid-State Circuits.

An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion

Young-Hyun Jun, Jeong-Don Ihm, Seung-Jun Bae, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

MetaCore: an application specific DSP development system

Kyu Ho Park, Young-Su Kwon, Chong-Min Kyung, 1998, DAC.

A Time-based Transceiver Front-end Circuit with 1-tap IIR DFE and Relaxed Termination for Short-reach PCB Interconnect

Hong-June Park, Min-Kyun Chae, Seung-Jun Bae, 2021 .

Aquabolt-XL: Samsung HBM2-PIM with in-memory processing for ML accelerators and beyond

Yuhwan Ro, Kyomin Sohn, Kwang-Il Park, 2021, 2021 IEEE Hot Chips 33 Symposium (HCS).

MetaCore: an application specific DSP development system

Young-Su Kwon, Chong-Min Kyung, Hyun-Dhong Yoon, 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).