P. Scheiblin

发表

FDSOI devices with thin BOX and ground plane integration for 32nm node and below

X. Garros, O. Faynot, C. Laviron, 2008, ESSDERC 2008 - 38th European Solid-State Device Research Conference.

Improved DIBL in Ultra Thin Body SOI MOSFETs with Ultra Thin Buried Oxide and inverted substrate

O. Faynot, Denis Flandre, Jean-Pierre Raskin, 2010 .

A novel locally engineered (111) V-channel pMOSFET architecture with improved drivability characteristics for low-standby power (LSTP) CMOS applications

F. Andrieu, T. Ernst, S. Deleonibus, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

Novel low temperature 3D wafer stacking technology for high density device integration

Sorin Cristoloveanu, Léa Di Cioccio, Thomas Signamarcheix, 2013, 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC).

Multi-$V_{T}$ UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

O. Rozeau, O. Faynot, M. Vinet, 2011, IEEE Transactions on Electron Devices.

UT2B-FDSOI device architecture dedicated to low power design techniques

O. Faynot, F. Andrieu, A. Amara, 2010, 2010 Proceedings of the European Solid State Device Research Conference.

Optimization of RF-22nm FDSOI figures of merit with 3D TCAD simulation

J. Mazurier, J. Lacord, D. Harame, 2017, 2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below

O. Rozeau, O. Faynot, M. Vinet, 2012, 2012 International Electron Devices Meeting.

193-nm scanner characterization by SEM and electrical CD measurements

Michel Heitzmann, A. Toffoli, Laurent Pain, 2000, Advanced Lithography.

Extending the functionality of FDSOI N- and P-FETs to light sensing

O. Rozeau, O. Faynot, M. Vinet, 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

In-depth physical investigation of GeOI pMOSFET by TCAD calibrated simulation

M. Vinet, P. Scheiblin, K. Romanjek, 2011 .

On the Influence of Fin Corner Rounding in 3D Nanocrystal Flash Memories

G. Reimbold, G. Ghibaudo, L. Perniola, 2008, 2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design.

TCAD for gate stack optimization in pGaN Gate HEMT devices

P. Scheiblin, Y. Baines, M. Charles, 2017, 2017 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD).

High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding

O. Rozeau, O. Faynot, F. Andrieu, 2008, 2008 IEEE International Electron Devices Meeting.

A simple and efficient concept for setting up multi-VT devices in thin BOx fully-depleted SOI technology

A. Amara, C. Fenouillet-Beranger, P. Scheiblin, 2009, 2009 Proceedings of the European Solid State Device Research Conference.

Doping of germanium by phosphorus implantation: Prediction of diffused profiles with simulation

S. Koffel, P. Scheiblin, V. Mazzocchi, 2008 .

High performance polysilicon nanowire NEMS for CMOS embedded nanosensors

T. Ernst, C. Reita, P. Scheiblin, 2014, 2014 IEEE International Electron Devices Meeting.

Amorphization kinetics of germanium during ion implantation

P. Scheiblin, Stéphane Koffel, P. Scheiblin, 2009 .

Dual channel and strain for CMOS co-integration in FDSOI device architecture

F. Andrieu, O. Weber, F. Allain, 2010, 2010 Proceedings of the European Solid State Device Research Conference.

High performance 70 nm gate length germanium-on-insulator pMOSFET with high-k/metal gate

X. Garros, G. Reimbold, Emmanuel Augendre, 2009 .

Drain / substrate coupling impact on DIBL of Ultra Thin Body and BOX SOI MOSFETs with undoped channel

O. Faynot, F. Andrieu, V. Kilchytska, 2009, 2009 Proceedings of the European Solid State Device Research Conference.

Methodology for predictive calibration of TCAD simulators

D. Poncet, P. Scheiblin, P. Rivallin, 1997, SISPAD '97. 1997 International Conference on Simulation of Semiconductor Processes and Devices. Technical Digest.