Akihiko Hashiguchi

FP 15.7: 5.4GOPS Linear Array Architecture DSP for Video-Format Conversion

Hiroshi Okuda, Takao Yamazaki, Masuyoshi Kurokawa, 1996 .

IEEE Symposium on Low-Power and High-Speed Chips

Josep Torrellas, Hideharu Amano, Masato Suzuki, 2011 .

Video DSP architecture and its application design methodology for sampling rate conversion

Hiroshi Okuda, Masuyoshi Kurokawa, Akihiko Hashiguchi, 1996, VLSI Signal Processing, IX.

Dynamic voltage and frequency management for a low-power embedded microprocessor

Takahiro Seki, Akihiko Hashiguchi, Katsunori Seno, 2005, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

A Programmable Video DSP Architecture for HDTV Applications

Hiroshi Okuda, Takao Yamazaki, Masuyoshi Kurokawa, 1996 .

5.4 GOPS, 81 GB/s Linear Array Architecture DSP

H. Hanaki, Masuyoshi Kurokawa, Akihiko Hashiguchi, 1998 .