Makoto Yabuuchi

发表

A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline

Koji Nii, Shinji Tanaka, Toshiaki Sano, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

A Robust Silicon-on-Insulator Static-Random-Access-Memory Architecture by using Advanced Actively Body-Bias Controlled Technology

Koji Nii, Y. Inoue, Hirofumi Shinohara, 2008 .

A 65 nm 1.0 V 1.84 ns Silicon-on-Thin-Box (SOTB) embedded SRAM with 13.72 nW/Mbit standby power for smart IoT

Koji Nii, Shinji Tanaka, Makoto Yabuuchi, 2017, 2017 Symposium on VLSI Technology.

A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias

Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique

Koji Nii, Jiro Ishikawa, Shinji Tanaka, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A 40-nm resilient cache memory for dynamic variation tolerance with bit-enhancing memory and on-chip diagnosis structures delivering ×91 failure rate improvement

Hiroyuki Kawai, Shunsuke Okumura, Yohei Nakata, 2014, Fifteenth International Symposium on Quality Electronic Design.

A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm2

Shunsuke Okumura, Makoto Yabuuchi, Kenichiro Hijioka, 2019, 2019 Symposium on VLSI Technology.

A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues

Hidehiro Fujiwara, Koji Nii, Yuichiro Ishii, 2012, 2012 IEEE 21st Asian Test Symposium.

A 6.05-Mb/mm2 16-nm FinFET double pumping 1W1R 2-port SRAM with 313 ps read access time

Koji Nii, Shinji Tanaka, Toshiaki Sano, 2016, 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits).

A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs

Hidehiro Fujiwara, Koji Nii, Shinji Tanaka, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die

Koji Nii, Koichiro Ishibashi, H. Makino, 2008, IEEE Journal of Solid-State Circuits.

A dynamic/static SRAM power management scheme for DVFS and AVS in advanced automotive infotainment SoCs

Koji Nii, Shinji Tanaka, Yuichiro Ishii, 2016, 2016 IEEE Symposium on VLSI Technology.

A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures

Hidehiro Fujiwara, Koji Nii, Shinji Tanaka, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A stable chip-ID generating physical uncloneable function using random address errors in SRAM

Hiroyuki Kawai, Hidehiro Fujiwara, Koji Nii, 2012, 2012 IEEE International SOC Conference.

A dynamic body-biased SRAM with asymmetric halo implant MOSFETs

Hidehiro Fujiwara, Koji Nii, Makoto Yabuuchi, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

International Symposium on Quality Electronic Design, ISQED 2013, Santa Clara, CA, USA, March 4-6, 2013

Hidehiro Fujiwara, Koji Nii, Houman Homayoun, 2013, ISQED.

A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure

Hidehiro Fujiwara, Koji Nii, Shinji Tanaka, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

Assessing uniqueness and reliability of SRAM-based Physical Unclonable Functions from silicon measurements in 45-nm bulk CMOS

Hidehiro Fujiwara, Koji Nii, Makoto Yabuuchi, 2014, Fifteenth International Symposium on Quality Electronic Design.

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations

Koji Nii, Hironori Akamatsu, Toshiyuki Oashi, 2008, IEEE Journal of Solid-State Circuits.

A 5.92-Mb/mm2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry

Koji Nii, Shinji Tanaka, Yuta Yoshida, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 29.2 Mb/mm2 Ultra High Density SRAM Macro using 7nm FinFET Technology with Dual-Edge Driven Wordline/Bitline and Write/Read-Assist Circuit

Yuichiro Ishii, Makoto Yabuuchi, Masao Morimoto, 2020, 2020 IEEE Symposium on VLSI Circuits.

Dependable SRAM with enhanced read-/write-margins by fine-grained assist bias control for low-voltage operation

Hiroyuki Kawai, Hidehiro Fujiwara, Koji Nii, 2010, 23rd IEEE International SOC Conference.

An implementation of 2RW dual-port SRAM using 65 nm Silicon-on-Thin-Box (SOTB) for smart IoT

Koji Nii, Shinji Tanaka, Yohei Sawada, 2017, 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

12-NM Fin-FET 3.0G-Search/s 80-Bit × 128-Entry Dual-Port Ternary CAM

Koji Nii, Shinji Tanaka, Makoto Yabuuchi, 2018, 2018 IEEE Symposium on VLSI Circuits.

Study of Local BTI Variation and its Impact on Logic Circuit and SRAM in 7 nm Fin-FET Process

Koji Shibutani, Makoto Yabuuchi, Yasumasa Tsukamoto, 2019, 2019 IEEE International Reliability Physics Symposium (IRPS).

A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

Koji Nii, Yohei Sawada, Yuichiro Ishii, 2018 .

A Ternary Based Bit Scalable, 8.80 TOPS/W CNN accelerator with Many-core Processing-in-memory Architecture with 896K synapses/mm2.

Shunsuke Okumura, Makoto Yabuuchi, Kenichiro Hijioka, 2019, 2019 Symposium on VLSI Circuits.

A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations

Koji Nii, Hiroshi Makino, Hironori Akamatsu, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

1.8 Mbit/mm2 ternary-CAM macro with 484 ps search access time in 16 nm Fin-FET bulk CMOS technology

Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

Embedded SRAM designs for enhancing performance, power and area (PPA) in 16 nm FinFET technology

Koji Nii, Shinji Tanaka, Toshiaki Sano, 2016, 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application

Hidehiro Fujiwara, Koji Nii, Tsu-Jae King Liu, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

A 40-nm Resilient Cache Memory for Dynamic Variation Tolerance Delivering ×91 Failure Rate Improvement under 35% Supply Voltage Fluctuation

Hiroyuki Kawai, Shunsuke Okumura, Yohei Nakata, 2014, IEICE Trans. Electron..

A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die

Koji Nii, Yuji Oda, Koichiro Ishibashi, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

A 65 nm 1.0 V 1.84 ns Silicon-on-Thin-Box (SOTB) embedded SRAM with 13.72 nW/Mbit standby power for smart IoT

Koji Nii, Shinji Tanaka, Makoto Yabuuchi, 2017, 2017 Symposium on VLSI Circuits.

40-nm 64-kbit Buffer/Backup SRAM with 330 nW Standby Power at 65°C Using 3.3 V IO MOSs for PMIC less MCU in IoT Applications

Koji Nii, Jiro Ishikawa, Daisuke Nakamura, 2018, 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC).

13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists

Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

A 7nm Fin-FET 4.04-Mb/mm2 TCAM with Improved Electromigration Reliability Using Far-Side Driving Scheme and Self-Adjust Reference Match-Line Amplifier

Makoto Yabuuchi, Yasumasa Tsukamoto, Masao Morimoto, 2020, 2020 IEEE Symposium on VLSI Circuits.

2RW dual-port SRAM design challenges in advanced technology nodes

Koji Nii, Shinji Tanaka, Takeshi Okagaki, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

Improving SRAM read/write margin with asymmetric halo MOSFET

Hidehiro Fujiwara, Koji Nii, Makoto Yabuuchi, 2011, 2011 International Semiconductor Device Research Symposium (ISDRS).

16 nm FinFET High-k/Metal-gate 256-kbit 6T SRAM macros with wordline overdriven assist

Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, 2014, 2014 IEEE International Electron Devices Meeting.