Yasumasa Tsukamoto

发表

A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline

Koji Nii, Shinji Tanaka, Toshiaki Sano, 2014, 2014 Symposium on VLSI Circuits Digest of Technical Papers.

A 0.41 µA Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS

Koji Nii, Yasuhisa Shimazaki, Koji Tanaka, 2013, IEEE Journal of Solid-State Circuits.

A Robust Silicon-on-Insulator Static-Random-Access-Memory Architecture by using Advanced Actively Body-Bias Controlled Technology

Koji Nii, Y. Inoue, Hirofumi Shinohara, 2008 .

A 0.5V 100MHz PD-SOI SRAM with enhanced read stability and write margin by asymmetric MOSFET and forward body bias

Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

28 nm 50% Power-Reducing Contacted Mask Read Only Memory Macro With 0.72-ns Read Access Time Using 2T Pair Bitcell and Dynamic Column Source Bias Control Technique

Koji Nii, Jiro Ishikawa, Shinji Tanaka, 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues

Hidehiro Fujiwara, Koji Nii, Yuichiro Ishii, 2012, 2012 IEEE 21st Asian Test Symposium.

A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs

Hidehiro Fujiwara, Koji Nii, Shinji Tanaka, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die

Koji Nii, Koichiro Ishibashi, H. Makino, 2008, IEEE Journal of Solid-State Circuits.

NBTI/PBTI separated BTI monitor with 4.2x sensitivity by standard cell based unbalanced ring oscillator

Koji Shibutani, Yasumasa Tsukamoto, Kan Takeuchi, 2017, 2017 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Optimization of importance sampling Monte Carlo using consecutive mean-shift method and its application to SRAM dynamic stability analysis

Yasumasa Tsukamoto, Yuji Kihara, Takeshi Kida, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures

Hidehiro Fujiwara, Koji Nii, Shinji Tanaka, 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

A stable chip-ID generating physical uncloneable function using random address errors in SRAM

Hiroyuki Kawai, Hidehiro Fujiwara, Koji Nii, 2012, 2012 IEEE International SOC Conference.

A dynamic body-biased SRAM with asymmetric halo implant MOSFETs

Hidehiro Fujiwara, Koji Nii, Makoto Yabuuchi, 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

A 28nm high density 1R/1W 8T-SRAM macro with screening circuitry against read disturb failure

Hidehiro Fujiwara, Koji Nii, Shinji Tanaka, 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations

Koji Nii, Hironori Akamatsu, Toshiyuki Oashi, 2008, IEEE Journal of Solid-State Circuits.

A 5.92-Mb/mm2 28-nm pseudo 2-read/write dual-port SRAM using double pumping circuitry

Koji Nii, Shinji Tanaka, Yuta Yoshida, 2016, 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC).

Dynamic stability in minimum operating voltage Vmin for single-port and dual-port SRAMs

Koji Nii, Shinji Tanaka, Koji Tanaka, 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

Full 3D Simulation of 6T-SRAM Cells for the 22nm Node

Xin Sun, Tsu-Jae King Liu, Changhwan Shin, 2009, 2009 International Conference on Simulation of Semiconductor Processes and Devices.

Worst-case analysis to obtain stable read/write DC margin of high density 6T-SRAM-array with local Vth variability

Koji Nii, Yuji Oda, Koichiro Ishibashi, 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..

Study of Local BTI Variation and its Impact on Logic Circuit and SRAM in 7 nm Fin-FET Process

Koji Shibutani, Makoto Yabuuchi, Yasumasa Tsukamoto, 2019, 2019 IEEE International Reliability Physics Symposium (IRPS).

Study of impact of BTI's local layout effect including recovery effect on various standard-cells in 10nm FinFET

Koji Nii, Koji Shibutani, Yasumasa Tsukamoto, 2018, 2018 IEEE International Reliability Physics Symposium (IRPS).

A Fully Standard-Cell Based On-Chip BTI and HCI Monitor with 6.2x BTI sensitivity and 3.6x HCI sensitivity at 7 nm Fin-FET Process

Koji Nii, Koji Shibutani, Yasumasa Tsukamoto, 2018, 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC).

A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues

Hidehiro Fujiwara, Koji Nii, Kazumasa Yanagisawa, 2010, IEEE Journal of Solid-State Circuits.

A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations

Koji Nii, Hiroshi Makino, Hironori Akamatsu, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

1.8 Mbit/mm2 ternary-CAM macro with 484 ps search access time in 16 nm Fin-FET bulk CMOS technology

Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, 2015, 2015 Symposium on VLSI Circuits (VLSI Circuits).

Embedded SRAM designs for enhancing performance, power and area (PPA) in 16 nm FinFET technology

Koji Nii, Shinji Tanaka, Toshiaki Sano, 2016, 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

3-D numerical modeling of thermal flow for insulating thin film using surface diffusion

Yasumasa Tsukamoto, Tetsuya Uchida, Tatsuya Kunikiyo, 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

Realistic Scaling Scenario for Sub-100 nm Embedded SRAM Based on 3-Dimensional Interconnect Simulation( the IEEE International Conference on SISPAD '02)

Koji Nii, Hiroshi Makino, Yasumasa Tsukamoto, 2003 .

A 32/spl times/24-bit multiplier-accumulator with advanced rectangular styled Wallace-tree structure

Koji Nii, Hiroshi Makino, Yasumasa Tsukamoto, 2005, 2005 IEEE International Symposium on Circuits and Systems.

Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application

Hidehiro Fujiwara, Koji Nii, Tsu-Jae King Liu, 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

Realization of Low-Power Dual-Port SRAM in 90 nm CMOS Technology with Self-Adjustable Sense-enable Generator Using Replica Ciruit

Koji Nii, T. Suzuki, Yasumasa Tsukamoto, 2003 .

A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die

Koji Nii, Yuji Oda, Koichiro Ishibashi, 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node

Tsu-Jae King Liu, Changhwan Shin, Yasumasa Tsukamoto, 2010, IEEE Transactions on Electron Devices.

Electrical Stability (Read and Write Operations)

Yasumasa Tsukamoto, Masanao Yamaoka, 2011 .

A 28 nm dual-port SRAM macro with screening circuitry against write-read disturb failure issues

Hidehiro Fujiwara, Koji Nii, Kazumasa Yanagisawa, 2010 .

13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists

Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

A 7nm Fin-FET 4.04-Mb/mm2 TCAM with Improved Electromigration Reliability Using Far-Side Driving Scheme and Self-Adjust Reference Match-Line Amplifier

Makoto Yabuuchi, Yasumasa Tsukamoto, Masao Morimoto, 2020, 2020 IEEE Symposium on VLSI Circuits.

2RW dual-port SRAM design challenges in advanced technology nodes

Koji Nii, Shinji Tanaka, Takeshi Okagaki, 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

International Symposium on Quality Electronic Design, ISQED 2013, Santa Clara, CA, USA, March 4-6, 2013

Hidehiro Fujiwara, Koji Nii, Houman Homayoun, 2013, ISQED.

Improving SRAM read/write margin with asymmetric halo MOSFET

Hidehiro Fujiwara, Koji Nii, Makoto Yabuuchi, 2011, 2011 International Semiconductor Device Research Symposium (ISDRS).

SRAM yield enhancement with thin-BOX FD-SOI

Borivoje Nikolic, Changhwan Shin, Yasumasa Tsukamoto, 2009, 2009 IEEE International SOI Conference.

16 nm FinFET High-k/Metal-gate 256-kbit 6T SRAM macros with wordline overdriven assist

Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, 2014, 2014 IEEE International Electron Devices Meeting.