Juanjo Noguera

发表

Xilinx First 7nm Device: Versal AI Core (VC1902)

Sagheer Ahmad, Sridhar Subramanian, Vamsi Boppana, 2019, 2019 IEEE Hot Chips 31 Symposium (HCS).

Improved Microarchitecture Support for Dynamic Task Scheduling on Reconfigurable Architectures

Juanjo Noguera, Zexin Pan, B. Earl Wells, 2005, ERSA.

Coarse-Grain Performance Estimator for Heterogeneous Parallel Computing Architectures like Zynq All-Programmable SoC pdf

Jan Langer, Juanjo Noguera, Xavier Martorell, 2015, ArXiv.

Configuration Prefetching for Non-deterministic Event Driven Multi-context Schedulers

Juanjo Noguera, Rosa M. Badia, 2000, FPL.

Session 9: Reconfigurable systems & tools for signal & image processing — Part 1

Juanjo Noguera, Diana Gohringer, 2011 .

System-level power-performance tradeoffs for reconfigurable computing

Juanjo Noguera, Rosa M. Badia, 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Fast Startup for Xilinx FPGAs

Juanjo Noguera, Jürgen Becker, Michael Hübner, 2011 .

Building real-time HDTV applications in FPGAs using processors, AXI interfaces and high level synthesis tools

Juanjo Noguera, Stephen Neuendorffer, Kees A. Vissers, 2011, 2011 Design, Automation & Test in Europe.

Performance and energy analysis of task-level graph transformation techniques for dynamically reconfigurable architectures

Juanjo Noguera, Rosa M. Badia, 2005, International Conference on Field Programmable Logic and Applications, 2005..

System-level power-performance trade-offs in task scheduling for dynamically reconfigurable architectures

Juanjo Noguera, Rosa M. Badia, 2003, CASES '03.

Power-performance trade-offs for reconfigurable computing

Juanjo Noguera, Rosa M. Badia, Juanjo Noguera, 2004, CODES+ISSS '04.

Fast Start-up for Spartan-6 FPGAs using Dynamic Partial Reconfiguration

Juanjo Noguera, Lars Braun, Jürgen Becker, 2011, 2011 Design, Automation & Test in Europe.

Software-programmable digital pre-distortion on new generation FPGAs

Jan Langer, Juanjo Noguera, Kees Vissers, 2014 .

Fast Sequential FPGA Startup Based on Partial and Dynamic Reconfiguration

Juanjo Noguera, Lars Braun, Jürgen Becker, 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

Power Reduction in Network Equipment Through Adaptive Partial Reconfiguration

Juanjo Noguera, Irwin O. Kennedy, Juanjo Noguera, 2007, 2007 International Conference on Field Programmable Logic and Applications.

Dynamic run-time HW/SW scheduling techniques for reconfigurable architectures

Juanjo Noguera, Rosa M. Badia, 2002, Proceedings of the Tenth International Symposium on Hardware/Software Codesign. CODES 2002 (IEEE Cat. No.02TH8627).

FPGA Startup Through Sequential Partial and Dynamic Reconfiguration

Juanjo Noguera, Lars Braun, Jürgen Becker, 2010, ISVLSI.

Heterogeneous tasking on SMP/FPGA SoCs: The case of OmpSs and the Zynq

Jan Langer, Juanjo Noguera, Daniel Jiménez-González, 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

Reconfigurable computing: an innovative solution for multimedia and telecommunication networks simulation

Jordi Domingo-Pascual, Juanjo Noguera, Rosa M. Badia, 1999, Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium.

Embedded Systems Start-Up under Timing Constraints on Modern FPGAs

Juanjo Noguera, Jürgen Becker, Joachim Meyer, 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

High-Level Synthesis for FPGAs: From Prototyping to Deployment

Jason Cong, Zhiru Zhang, Bin Liu, 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

A HW/SW partitioning algorithm for dynamically reconfigurable architectures

Juanjo Noguera, Rosa M. Badia, 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

Modelling and Performance Evaluation of a National Scale Switchless Based Network

Juanjo Noguera, Gabriel Junyent, Josep Solé-Pareta, 2000, INTERWORKING.

Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures

Nikil D. Dutt, Juanjo Noguera, Elaheh Bozorgzadeh, 2010, TRETS.

Development Framework for Implementing FPGA-Based Cognitive Network Nodes

Linda Doyle, Juanjo Noguera, Suhaib A. Fahmy, 2009, GLOBECOM 2009 - 2009 IEEE Global Telecommunications Conference.

Software-friendly HW/SW Co-Simulation: An Industrial Case Study

Juanjo Noguera, Lluis Abello, Luis Baldez, 2006, Proceedings of the Design Automation & Test in Europe Conference.

Fast dynamic and partial reconfiguration data path with low hardware overhead on Xilinx FPGAs

Juanjo Noguera, Jürgen Becker, Michael Hübner, 2010, 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW).

Power-Performance Trade-offs for Reconf i g u rable Corn pu t i ng

Juanjo Noguera, Rosa M. Badia, 2004 .

Minimizing peak power for application chains on architectures with partial dynamic reconfiguration

Nikil D. Dutt, Juanjo Noguera, Elaheh Bozorgzadeh, 2006, 2006 IEEE International Conference on Field Programmable Technology.

Run-time HW/SW codesign for discrete event systems using dynamically reconfigurable architectures

Juanjo Noguera, Rosa M. Badia, 2000, ISSS '00.

An FPGA-based cognitive radio framework

Linda Doyle, Juanjo Noguera, Suhaib A. Fahmy, 2008 .

Selective Band width and Resource Management in Scheduling for Dynamically Reconfigurable Architectures

Nikil D. Dutt, Juanjo Noguera, Elaheh Bozorgzadeh, 2007, 2007 44th ACM/IEEE Design Automation Conference.

Towards Novel Approaches in Design Automation for FPGA Power Optimization

Juanjo Noguera, Jürgen Becker, Michael Hübner, 2008, PATMOS.

HW/SW codesign techniques for dynamically reconfigurable architectures

Juanjo Noguera, Rosa M. Badia, 2002, IEEE Trans. Very Large Scale Integr. Syst..

SPECTRUM SENSING ON LTE FEMTOCELLS FOR GSM SPECTRUM RE-FARMING USING XILINX FPGAs

Linda Doyle, Juanjo Noguera, Suhaib A. Fahmy, 2009 .

Generic Software Framework for Adaptive Applications on FPGAs

Linda Doyle, Juanjo Noguera, Suhaib A. Fahmy, 2009, 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines.

Zynq-7000 All Programmable SoC Accelerator for Floating-Point Matrix Multiplication using Vivado HLS

Juanjo Noguera, Daniele Bagni, Fernando Martinez Vallina, 2013 .

Session 3: Reconfigurable systems & tools for signal & image processing — Part 1

Juanjo Noguera, Diana Gohringer, 2011 .

OmpSs@Zynq all-programmable SoC ecosystem

Jan Langer, Juanjo Noguera, Xavier Martorell, 2014, FPGA.

Iris: an architecture for cognitive radio networking testbeds

Linda Doyle, Juanjo Noguera, Hicham Lahlou, 2010, IEEE Communications Magazine.

A Model-Based Approach to Cognitive Radio Design

Linda Doyle, Juanjo Noguera, Suhaib A. Fahmy, 2011, IEEE Journal on Selected Areas in Communications.

Multitasking on reconfigurable architectures: microarchitecture support and dynamic scheduling

Juanjo Noguera, Rosa M. Badia, Juanjo Noguera, 2004, TECS.

HW/SW Codesign Techniques for Dynamically

Juanjo Noguera, Rosa M. Badia, 2002 .

Software-programmable digital pre-distortion on the Zynq SoC

Jan Langer, Juanjo Noguera, Kees A. Vissers, 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

Embedded Systems Start-Up under Timing Constraints on Modern FPGAs

Rodney Anthony Stewart, Juanjo Noguera, Jürgen Becker, 2011, International Conference on Field-Programmable Logic and Applications.

A HW/SW Codesign-Based Reconfigurable Environment for Telecommunication Network Simulation

Jordi Domingo-Pascual, Juanjo Noguera, Rosa M. Badia, 1999, FPL.

Implementation of sphere decoder for MIMO-OFDM on FPGAs using high-level synthesis tools

Juanjo Noguera, Stephen Neuendorffer, Chris Dick, 2011 .

Multi-platform demonstrations using the Iris architecture for cognitive radio network testbeds

Linda Doyle, Juanjo Noguera, Hicham Lahlou, 2010, 2010 Proceedings of the Fifth International Conference on Cognitive Radio Oriented Wireless Networks and Communications.

An FPGA-based Autonomous Adaptive Radio

Juanjo Noguera, Jörg Lotze, 2009 .