Dennis Walter

发表

Monadic dynamic logic: Application and implementation

Dennis Walter, Dennis Walter, 2005 .

An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS

Stephan Henker, Jens-Uwe Schluessler, René Schüffny, 2015, IEEE Journal of Solid-State Circuits.

Efficient compensation of delay variations in high-speed network-on-chip data links

René Schüffny, Dennis Walter, Sebastian Höppner, 2010, 2010 International Symposium on System on Chip.

A deep-submicron CMOS flow for general-purpose timing-detection insertion

René Schüffny, Dennis Walter, Sebastian Höppner, 2015, 2015 22nd International Conference Mixed Design of Integrated Circuits & Systems (MIXDES).

Energy Efficient Electrical Intra-Chip-Stack Communication

Johannes Gorner, Sebastian Hoppner, Dennis Walter, 2016 .

Integration of a Security Type System into a Program Logic

Reiner Hähnle, Jing Pan, Philipp Rümmer, 2006, TGC.

A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS

Gerhard Fettweis, Stephan Henker, René Schüffny, 2012, 2012 IEEE International Solid-State Circuits Conference.

A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM

Dennis Walter, Sebastian Höppner, Holger Eisenreich, 2020, 2020 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS).

Integration of a security type system into a program logic

Reiner Hähnle, Jing Pan, Philipp Rümmer, 2006, Theor. Comput. Sci..

Guaranteeing functional safety: design for provability and computer-aided verification

Christoph Lüth, Udo Frese, Dennis Walter, 2011, Autonomous Robots.

Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology

Stephan Henker, Jörg Schreiter, Dennis Walter, 2020, IEEE Transactions on Circuits and Systems II: Express Briefs.

Exploration of FPGA architectures for tight coupled accelerators in a 22nm FDSOI technology

Johannes Partzsch, Christian Mayr, Dennis Walter, 2017, 2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC).

Live demonstration: A 90GBit/s serial NoC link over 6mm in 65nm CMOS technology

René Schüffny, Dennis Walter, Sebastian Höppner, 2013, 2013 European Conference on Circuit Theory and Design (ECCTD).

An MPSoC for energy-efficient database query processing

Gerhard Fettweis, Yong Chen, Stephan Henker, 2016, 2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC).

Experiences in Applying Formal Verification in Robotics

Christoph Lüth, Dennis Walter, Holger Täubig, 2010, SAFECOMP.

A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology

Stephan Henker, René Schüffny, Dennis Walter, 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS

Gerhard Fettweis, Stephan Hartmann, Sebastian Hoppner, 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

The Importance of Being Formal

Christoph Lüth, Udo Frese, Dennis Walter, 2009, Electron. Notes Theor. Comput. Sci..

A physical synthesis flow for early technology evaluation of silicon nanowire based reconfigurable FETs

Akash Kumar, Christian Mayr, Dennis Walter, 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

An energy efficient multi-bit TSV transmitter using capacitive coupling

Johannes Gorner, René Schüffny, Michael Haas, 2014, 2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS).

How to Achieve World-Leading Energy Efficiency using 22FDX with Adaptive Body Biasing on an Arm Cortex-M4 IoT SoC

Dennis Walter, Sebastian Höppner, Holger Eisenreich, 2019, ESSDERC 2019 - 49th European Solid-State Device Research Conference (ESSDERC).

A heterogeneous SDR MPSoC in 28nmCMOS for low-latency wireless applications

Gerhard Fettweis, Norbert Wehn, Yong Chen, 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology

René Schüffny, Dennis Walter, Sebastian Höppner, 2013, IEEE Transactions on Circuits and Systems II: Express Briefs.

Certifiable Specification and Verification of C Programs

Christoph Lüth, Dennis Walter, Christoph Lüth, 2009, FM.

Zertifizierung einer Sicherungskomponente mittels durchgängig formaler Modellierung

Christoph Lüth, Udo Frese, Dennis Walter, 2008, Software Engineering.

Exploiting transistor-level reconfiguration to optimize combinational circuits

Akash Kumar, Marcus Völp, Thomas Mikolajick, 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

Clock Generators for Heterogeneous MPSoCs Within 3D Chip Stacks

Sebastian Hoppner, Rene Schuffny, Dennis Walter, 2016 .

A formal verification environment for use in the certification of safety-related C-programs

Dennis Walter, Dennis Walter, 2010 .

On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links

René Schüffny, Dennis Walter, Sebastian Höppner, 2012, Int. J. Embed. Real Time Commun. Syst..

Mismatch characterization of high-speed NoC links using asynchronous sub-sampling

René Schüffny, Dennis Walter, Sebastian Höppner, 2011, 2011 International Symposium on System on Chip (SoC).

Parametrized Exceptions

Till Mossakowski, Lutz Schröder, Dennis Walter, 2005, CALCO.

The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing pdf

Jim D. Garside, Steve B. Furber, Johannes Partzsch, 2021, ArXiv.

Hardware Implementation of an OPC UA Server for Industrial Field Devices

Leon Urbas, Chris Iatrou, Christian Mayr, 2021, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

Energy efficiency enhancements for semiconductors, communications, sensors and software achieved in cool silicon cluster project

Gerhard Fettweis, Corrado Carta, Frank Ellinger, 2013 .