W. C. Chien

A novel conducting bridge resistive memory using a semiconducting dynamic E-field moderating layer

F. M. Lee, Y. Y. Lin, W. C. Chien, 2013, 2013 Symposium on VLSI Technology.

A Procedure to Reduce Cell Variation in Phase Change Memory for Improving Multi-Level-Cell Performances

W. C. Chien, M. H. Lee, H. L. Lung, 2015, 2015 IEEE International Memory Workshop (IMW).

A novel inspection and annealing procedure to rejuvenate phase change memory from cycling-induced degradations for storage class memory applications

W. C. Chien, M. H. Lee, H. L. Lung, 2014, 2014 IEEE International Electron Devices Meeting.

Greater than 2-bits/cell MLC storage for ultra high density phase change memory using a novel sensing scheme

W. C. Chien, M. H. Lee, H. L. Lung, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

A novel self-converging write scheme for 2-bits/cell phase change memory for Storage Class Memory (SCM) application

W. C. Chien, H. L. Lung, C. J. Chen, 2015, 2015 Symposium on VLSI Technology (VLSI Technology).

A novel cross point one-resistor (0T1R) conductive bridge random access memory (CBRAM) with ultra low set/reset operation current

F. M. Lee, Y. Y. Lin, W. C. Chien, 2012, 2012 Symposium on VLSI Technology (VLSIT).

Towards the integration of both ROM and RAM functions phase change memory cells on a single die for system-on-chip (SOC) applications

W. C. Chien, H. L. Lung, J. Y. Wu, 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.