Churoo Park

Three-Dimensional Integration Approach to High-Density Memory Devices

U-In Chung, Hojung Kim, Sanghun Jeon, 2011, IEEE Transactions on Electron Devices.

A 512 Mbit, 1.6 Gbps/pin DDR3 SDRAM prototype with C/sub 10/ minimization and self-calibration techniques

Soo-In Cho, Jae-Kwan Kim, Yun-Sang Lee, 2005, Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005..

A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system

Hyoungsik Nam, Hyun-Jun Yoon, Churoo Park, 1998, IEEE J. Solid State Circuits.

16 Mbit synchronous DRAM with 125 Mbyte/sec data rate

Tae-Jin Kim, Soo-In Cho, Seung-Hoon Lee, 1993, Symposium 1993 on VLSI Circuits.

Co-Architecting Controllers and DRAM to Enhance DRAM Process Scaling

Hongzhong Zheng, Churoo Park, Seong-Jin Jang, 2014 .

Skew minimization techniques for 256M-bit synchronous DRAM and beyond

Seung-Hoon Lee, Jin-Man Han, Churoo Park, 1996 .

An Area-Efficient, Low-VDD, Highly Reliable Multi-Cell Antifuse System Fully Operative in DRAMs

Soo-Won Kim, Young-Hyun Jun, Jong-Pil Son, 2011, IEICE Trans. Electron..

A highly reliable multi-cell antifuse scheme using DRAM cell capacitors

Soo-Won Kim, Young-Hyun Jun, Jong-Pil Son, 2010, 2010 Proceedings of ESSCIRC.

A 512-Mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques

Soo-In Cho, Seung-Hoon Lee, Jae-Kwan Kim, 2006, VLSIC 2006.

16-Mb synchronous DRAM with 125-Mbyte/s data rate

Tae-Jin Kim, Soo-In Cho, Seung-Hoon Lee, 1994 .